參數(shù)資料
型號: 9250BF-28LF-T
廠商: INTEGRATED DEVICE TECHNOLOGY INC
元件分類: 時鐘產(chǎn)生/分配
英文描述: 133.32 MHz, PROC SPECIFIC CLOCK GENERATOR, PDSO56
封裝: 0.300 INCH, GREEN, SSOP-56
文件頁數(shù): 14/19頁
文件大?。?/td> 226K
代理商: 9250BF-28LF-T
4
ICS9250-28
Byte 3: ICS Reserved Functionality and frequency select register (Default as noted in PWD)
2
S
F0
S
F1
S
FU
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6
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3
Truth Table
Note 1: For system operation, the BSEL lines of the CPU will program FS0, FS2 for the appropriate CPU speed, always
with SDRAM = 100MHz. After BIOS verifies the SDRAM is PC133 speed, then bit 0 can be written from the
default 0 to 1 to change the SDRAM output frequency from 100MHz to 133MHz. This will only change if the
CPU is at the 133MHz FSB speed as shown in this table. The CPU, 3V66, PCI, and IOAPIC clocks will be glitch
free during this transition, and only SDRAM will change.
Note 2: "ICS RESERVED BITS" must be writtern as "0".
Note3: Undefined bits can be written either as "1 or 0"
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