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參數(shù)資料
| 型號： | 9148F-18 |
| 廠商： | INTEGRATED DEVICE TECHNOLOGY INC |
| 元件分類： | 時鐘產(chǎn)生/分配 |
| 英文描述： | 100 MHz, PROC SPECIFIC CLOCK GENERATOR, PDSO28 |
| 封裝： | 0.209 INCH, SSOP-28 |
| 文件頁數(shù)： | 1/12頁 |
| 文件大?。?/td> | 285K |
| 代理商： | 9148F-18 |
Integrated
Circuit
Systems, Inc.
General Description
Features
ICS9148-18
Block Diagram
Pentium/ProTM System Clock Chip
9148-18 Rev C 12/02/05
Pin Configuration
28 pin SSOP
Pentium is a trademark on Intel Corporation.
Generates system clocks for CPU, PCI,
plus 14.314 MHz REF0.
Supports single or dual processor systems
Skew from CPU (earlier) to PCI clock (rising edges for
100/33.3MHz) 1 to 4ns
Separate 2.5V and 3.3V supply pins
2.5V or 3.3V output: CPU
3.3V outputs: PCI, REF
No power supply sequence requirements
Uses external 14.318MHz crystal, no external load cap
required for CL=18pF crystal
28 pin 209 mil SSOP
The ICS9148-18 is a Clock Synthesizer chip for Pentium and
PentiumPro CPU based Desktop/Notebook systems that will
provide all necessary clock timing.
Features include two CPU and six PCI clocks. One reference
output is available equal to the crystal frequency. Additionally,
the device meets the Pentium power-up stabilization
requirement, acheiving stable CPU and PCI clocks 2ms after
power-up.
PD# pin can enable a low power mode by stopping crystal
OSC and PLL stages. Other power management features
include, CPU_STOP# which stops CPU (0:1) clocks, and
PCI_STOP# which stops PCICLK (0:4) clocks.
High drive CPUCLK outputs typically provide greater than 1
V/ns slew rate into 20pF loads. PCICLK outputs typically
provide better than 1V/ns slew rate into 30pF loads while
maintaining 50±5% duty cycle. The REF clock output typically
provides better than 0.5V/ns slew rates.
The ICS9148-18 accepts a 14.318MHz reference crystal or
clock as its input and runs on a 3.3V core supply.
Ground Groups
GND = Ground Source Core
GND1 = REF0, X1, X2
GND2 = PCICLK_F, PCICLK (0:4)
GNDL=CPUCLK(0:1)
Power Groups
VDD = Supply for PLL core
VDD1 = REF0, X1, X2
VDD2 = PCICLK_F, PCICLK (0:4)
VDDL=CPUCLK(0:1)
ICS reserves the right to make changes in the device data identified in this
publication without further notice. ICS advises its customers to obtain the latest
version of all device data to verify that any information being relied upon by the
customer is current and accurate.
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