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參數(shù)資料
| 型號(hào)： | 9240LPRPQB |
| 廠商： | MAXWELL TECHNOLOGIES |
| 元件分類： | ADC |
| 英文描述： | 1-CH 14-BIT PROPRIETARY METHOD ADC, PARALLEL ACCESS, QFP44 |
| 封裝： | RAD-PAK, QFP-44 |
| 文件頁數(shù)： | 8/10頁 |
| 文件大?。?/td> | 189K |
| 代理商： | 9240LPRPQB |
Memory
7
All data sheets are subject to change without notice
2002 Maxwell Technologies
All rights reserved.
14-Bit, 10 MSPS Monolithic A/D Converter with LPT ASIC
9240LP
03.08.02 Rev 4
TABLE 6. 9240LP DIGITAL SPECIFICATIONS
(AVDD = 5V, DVDD = 5V, T
A = -55 TO +125°C, UNLESS OTHERWISE SPECIFIED)
PARAMETER
SYMBOL
SUBGROUPS
MIN
TYP
MAX
UNIT
CLOCK INPUT
High Level Input Voltage1
Low Level Input Voltage1
High Level Input Current (V
IN = DVDD)
Low Level Input Current (V
IN = 0V)
Input Capacitance
1. Guaranteed by design.
V
IH
V
IL
I
IH
I
IL
C
IN
1, 2, 3
--
5
3.5
1.0
±10
--
V
A
pF
LOGIC OUTPUTS (with DRVDD = 5V)
High Level Output Voltage (I
OH = 50 A)
High Level Output Voltage (I
OH = 0.5 mA)
Low Level Output Voltage (I
OL = 1.6 mA)
Low Level Output Voltage (I
OL = 50 A)
Output Capacitance1
V
OH
V
OH
V
OL
V
OL
C
OUT
1, 2, 3
4.5
2.4
--
5
--
0.4
0.1
--
V
pF
TABLE 7. 9240LP SWITCHING CHARACTERISTICS1
(T
A = -55 TO +125°C WITH AVDD = 5V, DVDD = 5V, DRVDD = 5V, RBIAS = 2 KW, CL = 20 PF)
1. Guaranteed by design.
TIMING DIAGRAM
PARAMETER
SYMBOL
MIN
TYP
MAX
UNITS
Clock Period
CLOCK Pulse width High
CLOCK Pulse width Low
Output Delay
Pipeline Delay (Latency)
t
C
t
CH
t
CL
t
OD
100
45
8
--
13
3
--
19
--
ns
Clock Cycles
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