參數(shù)資料
型號： 9214YGLF-T
廠商： INTEGRATED DEVICE TECHNOLOGY INC
元件分類： 時(shí)鐘及定時(shí)
英文描述： 9214 SERIES, PLL BASED CLOCK DRIVER, 4 TRUE OUTPUT(S), 0 INVERTED OUTPUT(S), PDSO28
封裝： 4.40 MM, 0.65 MM PITCH, LEAD FREE, MO-153, TSSOP-28
文件頁數(shù)： 16/16頁
文件大?。?/td> 224K
代理商： 9214YGLF-T
9
Integrated
Circuit
Systems, Inc.
ICS9214
0809G—08/02/08
AC Characteristics-Inputs
TA = 0°C to +85°C; Supply Voltage AVDD2.5, VDD2.5 = 2.5 V +/- 0.125V (unless otherwise stated)
PARAMETER
SYMBOL
CONDITION
MIN
TYP
MAX
UNITS
CLK_INT/CLK_INC cycle
time
1
tCYCLEIN
711
ns
Cycle-to-Cycle Jitter
tcyc-tcyc
2
185
ps
Input clock duty cycle
dtin
over 10,000 cycles
40
60
%
CLK_INT/CLK_INC rise and
fall time
tR, tF
20% to 80% of input
voltage
175
700
ps
Difference between input rise
and fall time on same pin of a
single device
tR-F
20% to 80% of input
voltage
-
150
ps
Spread spectrum modulation
frequency
fINM
3
30
33
kHz
Triangular modulation
0.6
%
Non-triangular modulation
0.54
%
Input clock slew rate
tsl(I)
20% to 80% of input
voltage
14
V/ns
Input Capacitance
5
CINCLK
CLK_INT, CLK_INC
7
pF
Input Capacitance
5
CIN
VI = VDD2.5 or GND
10
pF
CLK_INT cycle time
tCYCLETST
Bypass Mode
4
40
ns
SMBus clock frequency
fSMB
10
100
kHz
Notes:
4. The amount of allowed spreading for non-triangular modulation is determined
by the induced downstream tracking skew.
5. Capacitance measured at f = 1 MHz, DC bias = 0.9V, VAC <100mV.
3. If input modulation is used. Input modulation is not necessary.
mINDEX
3
Spread spectrum modulation
index
1. Measured at (VIH(nom) - VIL(nom))/2 and is the absolute value of the worst case deviation.
2. Measured at crossing points for differential clock input or at VTH for single-ended clock input
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