參數(shù)資料
型號: 9214YGLF-T
廠商: INTEGRATED DEVICE TECHNOLOGY INC
元件分類: 時鐘及定時
英文描述: 9214 SERIES, PLL BASED CLOCK DRIVER, 4 TRUE OUTPUT(S), 0 INVERTED OUTPUT(S), PDSO28
封裝: 4.40 MM, 0.65 MM PITCH, LEAD FREE, MO-153, TSSOP-28
文件頁數(shù): 15/16頁
文件大小: 224K
代理商: 9214YGLF-T
8
Integrated
Circuit
Systems, Inc.
ICS9214
0809G—08/02/08
DC Characteristics - Outputs
TA = 0°C to +85°C; Supply Voltage AVDD2.5, VDD2.5 = 2.5 V +/- 0.125V (unless otherwise stated)
PARAMETER
SYMBOL
CONDITIONS
MIN
TYP
MAX
UNITS
Power up latency
tPU
Power within spec to
outputs within spec
3ms
State transition latency
1
tCO
SMBus or Mode Select
transition to outputs valid
and within spec
3ms
Differential output
crossing voltage
VOX
Measured as shown in Fig.
3
0.9
1.1
V
Output Voltage Swing
(peak-to-peak singled
ended)
VCOS
Measured as shown in Fig.
3. Excludes over and
undershoot.
300
350
mV
Absolute output low voltage
VOLABS
Measured at ODCLK_T/C
pins
0.85
V
Reference Voltage for
swing control current
VISET
VDD = 2.3V, VOUT = 1V
0.98
1.02
V
Ratio of output low
current to reference
current at typical VDD2.5
IOL/IREF
IREF is equal to VISET/RRC.
Tolerance of RRC <=+/-1%.
6.8
7
7.2
-
Minimum current at
VOLABS
IOLABS
Measured at ODCLK_T/C
pins with termination per
Figure 3.
45
-
mA
Low-level output voltage
SMBus
VOLSMB
IOL = 4 mA
-0.4
V
Low-level output current
SMBus
IOLSMB
VOL= 0.8 V
6-
mA
Tristate output current
IOZ
Differential clock output pins
-
50
Α
Notes:
There is no output latency or glitches if a value is written to an output register.
that is the same as its current contents.
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