參數(shù)資料
型號(hào): 9112BM-17LF-T
廠商: INTEGRATED DEVICE TECHNOLOGY INC
元件分類: 時(shí)鐘及定時(shí)
英文描述: 9112 SERIES, LOW SKEW CLOCK DRIVER, 8 TRUE OUTPUT(S), 0 INVERTED OUTPUT(S), PDSO16
封裝: 0.150 INCH, ROHS COMPLIANT, MS-012, SOIC-16
文件頁(yè)數(shù): 5/9頁(yè)
文件大?。?/td> 1473K
代理商: 9112BM-17LF-T
5
ICS9112-17
0051L—08/03/07
Output to Output Skew
The skew between CLKOUT and the CLKA/B outputs is not dynamically adjusted by the PLL. Since CLKOUT is one
of the inputs to the PLL, zero phase difference is maintained from REF to CLKOUT. If all outputs are equally loaded,
zero phase difference will maintained from REF to all outputs.
If applications requiring zero output-output skew, all the outputs must equally loaded.
If the CLKA/B outputs are less loaded than CLKOUT, CLKA/B outputs will lead it; and if the CLKA/B is more loaded
than CLKOUT, CLKA/B will lag the CLKOUT.
Since the CLKOUT and the CLKA/B outputs are identical, they all start at the same time, but different loads cause them
to have different rise times and different times crossing the measurement thresholds.
REF input and
all outputs
loaded Equally
REF input and CLKA/B
outputs loaded equally, with
CLKOUT loaded More.
REF input and CLKA/B
outputs loaded equally, with
CLKOUT loaded Less.
Timing diagrams with different loading configurations
相關(guān)PDF資料
PDF描述
9112M-33 106.25 MHz, OTHER CLOCK GENERATOR, PDSO8
9112YG-27-T 9112 SERIES, LOW SKEW CLOCK DRIVER, 4 TRUE OUTPUT(S), 0 INVERTED OUTPUT(S), PDSO8
9112YM-27T 9112 SERIES, LOW SKEW CLOCK DRIVER, 4 TRUE OUTPUT(S), 0 INVERTED OUTPUT(S), PDSO8
9112YG-27T 9112 SERIES, LOW SKEW CLOCK DRIVER, 4 TRUE OUTPUT(S), 0 INVERTED OUTPUT(S), PDSO8
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