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參數(shù)資料
| 型號： | 9112YG-27T |
| 廠商： | INTEGRATED DEVICE TECHNOLOGY INC |
| 元件分類： | 時鐘及定時 |
| 英文描述： | 9112 SERIES, LOW SKEW CLOCK DRIVER, 4 TRUE OUTPUT(S), 0 INVERTED OUTPUT(S), PDSO8 |
| 封裝： | 0.173 INCH, MO-153, LEAD FREE, TSSOP-8 |
| 文件頁數(shù)： | 1/8頁 |
| 文件大?。?/td> | 1439K |
| 代理商： | 9112YG-27T |
Integrated
Circuit
Systems, Inc.
General Description
Features
ICS9112-27
0055G—04/26/05
Block Diagram
Low Skew PCI / PCI-X Buffer
Pin Configuration
Frequency range 0 - 140 MHz (3.3V)
Less than 200 ps Jitter between outputs
Skew controlled outputs < 100 ps
Distribute one clock input to one bank of four
outputs
3.3V ±10% operation
Available in 8 pin TSSOP, and SOIC packages.
The ICS9112-27 is a high performance, low skew, low jitter
PCI / PCI-X clock driver. It is designed to distribute high
speed signals in PCI / PCI-X applications operating at
speeds from 0 to 140 MHz.
The ICS9112-27 is characterized for operation from -40°C
to 85°C for automotive and industrial applications.
8 pin TSSOP & SOIC
CLK_IN
OE
CLK0
GND
CLK3
CLK2
VDD
CLK1
ICS9112-27
1
2
3
4
8
7
6
5
CLK_IN
CLK0
CLK1
CLK2
CLK3
LOGIC
CONTROL
OE
Pin Descriptions
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Functionality Table
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