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February 15, 2006
2006 Integrated Device Technology, Inc.
DSC 6801
IDT and the IDT logo are trademarks of Integrated Device Technology, Inc.
Devic e Overview
The PES12N3, a 12 lane 3-port PCI Expressswitch, is a member
of IDT’s PRECISE famly of PCI Express switching solutions. The
PES12N3 is a peripheral chip that performs PCI Express Base switching
with a feature set optimzed for high performance applications such as
servers and storage. It provides connectivity and switching functions
between a PCI Express upstreamport and two downstreamports or
peer-to-peer switching between downstreamports.
Features
High Performance PCI Express Switch
– Three x4 ports with 12 PCI lanes total
– Delivers 6 GBps (48 Gbps) aggregate switching capacity
– Low latency cut-through switch architecture
– Supports 128
to
256 byte maximumpayload size
– Supports one virtual channel
– PCI Express Base specification Revision 1.0a compliant
◆
Flexible Architecture with Numerous Configuration Options
– Port arbitration schemes utilizing round robin or weighted
round robin algorithms
– Supports automatic per port link with negotiation (x4, x2, or x1)
– Supports static lane reversal on all ports
– Supports polarity inversion
– Supports locked transactions, allowing use with legacy soft-
ware
– Ability to load device configuration fromserial EEPROM
◆
Highly Integrated Solution
– Requires no external components
– Incorporates on-chip internal memory for packet buffering and
queueing
– Integrates 12 2.5 Gbps embedded SerDes, 8B/10B encoder/
decoder (no separate transceivers needed)
◆
Reliability, Availability, and Serviceability (RAS) Features
– Internal end-to-end parity protection on all TLPs ensures data
integrity even in systems that do not implement end-to-end
CRC (ECRC)
– Supports ECRC passed through
– Supports PCI Express Native Hot-Plug
Compatible with Hot-Plug I/O expanders used on PC moth-
erboards
– Supports Hot-Swap
◆
Power Management
– Supports PCI Express Power Management Interface Specifi-
cation, Revision 1.1 (PCI-PM)
– Unused SerDes are disabled
– Supports Advanced Configuration and Power Interface Speci-
fication, Revision 2.0 (ACPI) supporting active link state
◆
Testability and Debug Features
– Supports IEEE 1149.6 JTAG
– Built in SerDes Pseudo-RandomBit Stream(PRBS) generator
– Ability to read and write any internal register via the SMBus
– Ability to bypass link training and force any link into any mode
– Provides statistics and performance counters
Block Diagram
12 PCI Express Lanes
One x4 Upstream Port and T wo x4 Downstream Ports
3-Port Switch Core
Frame Buffer
Scheduler
Multiplexer/Demultiplexer
Transaction Layer
Data Link Layer
Route Table
Port
Arbitration
SerDes
Phy
Logical
Layer
SerDes
Phy
Logical
Layer
SerDes
Phy
Logical
Layer
Multiplexer/Demultiplexer
Transaction Layer
Data Link Layer
SerDes
Phy
Logical
Layer
SerDes
Phy
Logical
Layer
SerDes
Phy
Logical
Layer
Multiplexer/Demultiplexer
Transaction Layer
Data Link Layer
SerDes
Phy
Logical
Layer
SerDes
Phy
Logical
Layer
SerDes
Phy
Logical
Layer
SerDes
Phy
Logical
Layer
SerDes
Phy
Logical
Layer
SerDes
Phy
Logical
Layer
89PES12N3
Product Brief
12 Lane 3-Port PCI Express Switch