參數(shù)資料
型號: 89PES32T8
廠商: Integrated Device Technology, Inc.
英文描述: 32-Lane 8-Port PCI Express㈢Switch
中文描述: 32巷8端口的PCI Express㈢開關(guān)
文件頁數(shù): 1/2頁
文件大?。?/td> 57K
代理商: 89PES32T8
1 of 2
February 8, 2007
2007 Integrated Device Technology, Inc.
IDT and the IDT logo are trademarks of Integrated Device Technology, Inc.
Devic e Overview
The 89HPES32T8 is a member of the IDT PRECISE famly of PCI
Expressswitching solutions. The PES32T8 is a 32-lane, 8-port periph-
eral chip that performs PCI Express Packet switching with a feature set
optimzed for high performance applications such as servers, storage,
and communications/networking. It provides connectivity and switching
functions between a PCI Express upstreamport and up to seven down-
streamports and supports switching between downstreamports.
Features
High Performance PCI Express Switch
Thirty-two 2.5 Gbps PCI Express lanes
Eight switch ports
Upstreamport configurable up to x8
Downstreamports configurable up to x8
Low-latency cut-through switch architecture
Support for Max Payload Size up to 2048 bytes
One virtual channel
Eight traffic classes
PCI Express Base Specification Revision 1.1 compliant
Flexible Architecture with Numerous Configuration Options
Automatic per port link width negotiation to x8, x4, x2 or x1
Automatic lane reversal on all ports
Automatic polarity inversion on all lanes
Ability to load device configuration fromserial EEPROM
Legacy Support
PCI compatible INTx emulation
Bus locking
Highly Integrated Solution
Requires no external components
Incorporates on-chip internal memory for packet buffering and
queueing
Integrates thirty-two 2.5 Gbps embedded SerDes with 8B/10B
encoder/decoder (no separate transceivers needed)
Reliability, Availability, and Serviceability (RAS) Features
Supports ECRC and Advanced Error Reporting
Internal end-to-end parity protection on all TLPs ensures data
integrity even in systems that do not implement end-to-end
CRC (ECRC)
Supports PCI Express Native Hot-Plug, Hot-Swap capable I/O
Compatible with Hot-Plug I/O expanders used on PC and
server motherboards
Power Management
Utilizes advanced low-power design techniques to achieve low
typical power consumption
Supports PCI Power Management Interface specification
(PCI-PM1.1)
Supports device power management states: D0, D3
hot
and
D3
cold
Unused SerDes are disabled
Block Diagram
Figure 1 Internal Block Diagram
8-Port Switch Core / 32 PCI Express Lanes
Frame Buffer
Route Table
Port
Arbitration
Scheduler
SerDes
Phy
Logical
Layer
SerDes
Phy
Logical
Layer
SerDes
Phy
Logical
Layer
Multiplexer / Demultiplexer
Transaction Layer
Data Link Layer
SerDes
Phy
Logical
Layer
SerDes
Phy
Logical
Layer
SerDes
Phy
Logical
Layer
SerDes
Phy
Logical
Layer
Multiplexer / Demultiplexer
Transaction Layer
Data Link Layer
SerDes
Phy
Logical
Layer
SerDes
Phy
Logical
Layer
SerDes
Phy
Logical
Layer
SerDes
Phy
Logical
Layer
Multiplexer / Demultiplexer
Transaction Layer
Data Link Layer
SerDes
Phy
Logical
Layer
(Port 0)
(Port 1)
(Port 7)
89PES32T8
Product Brief
32-Lane 8-Port PCI Express
Switch
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