參數(shù)資料
型號： 87LPC767
廠商： NXP Semiconductors N.V.
英文描述： Low power, low price, low pin count(20 pin) microcontroller with 4 kB OTP and 8-bit A/D(帶4 kB OTP和8位A/D的低功耗，低價格，少引腳（20引腳）的微控制器)
中文描述： 低功耗，低價格，低引腳數(shù)（20針）與4 KB的檢察官辦公室和8位A / D（帶4 KB的檢察官和8位A / D轉(zhuǎn)換的低功耗，低價格，少引腳（20引微控制器腳）的微控制器）
文件頁數(shù)： 26/61頁
文件大?。?/td> 296K
代理商： 87LPC767
Philips Semiconductors
Preliminary specification
87LPC767
Low power, low price, low pin count (20 pin)
microcontroller with 4 kB OTP and 8-bit A/D converter
2000 Feb 02
23
BIT
P2M1.7
P2M1.6
P2M1.5
P2M1.4
SYMBOL
P2S
P1S
P0S
ENCLK
FUNCTION
When P2S = 1, this bit enables Schmitt trigger inputs on Port 2.
When P1S = 1, this bit enables Schmitt trigger inputs on Port 1.
When P0S = 1, this bit enables Schmitt trigger inputs on Port 0.
When ENCLK is set and the 87LPC764 is configured to use the on-chip RC oscillator, a clock
output is enabled on the X2 pin (P2.0). Refer to the Oscillator section for details.
When set, the P.7 pin is toggled whenever Timer 1 overflows. The output frequency is therefore
one half of the Timer 1 overflow rate. Refer to the Timer/Counters section for details.
When set, the P1.2 pin is toggled whenever Timer 0 overflows. The output frequency is therefore
one half of the Timer 0 overflow rate. Refer to the Timer/Counterssection for details.
These bits, along with the matching bits in the P2M2 register, control the output configuration of
P2.1 and P2.0 respectively, as shown in Table 4.
P2M1.3
ENT1
P2M1.2
ENT0
P2M1.1, P2M1.0
—
(P2M1.0)
SU01162
(P2M1.1)
ENT0
ENT1
ENCLK
P0S
P1S
P2S
0
1
2
3
4
5
6
7
P2M1
Reset Value: 00h
Not Bit Addressable
Address: A4h
Figure 15. Port 2 Mode Register 1 (P2M1)
Keyboard Interrupt (KBI)
The Keyboard Interrupt function is intended primarily to allow a
single interrupt to be generated when any key is pressed on a
keyboard or keypad connected to specific pins of the 87LPC767, as
shown in Figure 16. This interrupt may be used to wake up the CPU
from Idle or Power Down modes. This feature is particularly useful in
handheld, battery powered systems that need to carefully manage
power consumption yet also need to be convenient to use.
The 87LPC767 allows any or all pins of port 0 to be enabled to
cause this interrupt. Port pins are enabled by the setting of bits in
the KBI register, as shown in Figure 17. The Keyboard Interrupt Flag
(KBF) in the AUXR1 register is set when any enabled pin is pulled
low while the KBI interrupt function is active. An interrupt will
generated if it has been enabled. Note that the KBF bit must be
cleared by software.
Due to human time scales and the mechanical delay associated with
keyswitch closures, the KBI feature will typically allow the interrupt
service routine to poll port 0 in order to determine which key was
pressed, even if the processor has to wake up from Power Down
mode. Refer to the section on Power Reduction Modes for details.
相關(guān)PDF資料
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