參數(shù)資料
型號： 87C529
廠商： NXP Semiconductors N.V.
英文描述： 80C51 9-bit microcontrollers(80C51 9位微控制器)
中文描述： 80C51的8位微控制器（80C51的8位微控制器）
文件頁數(shù)： 6/26頁
文件大?。?/td> 266K
代理商： 87C529
Philips Semiconductors
Product specification
87C524/87C528
80C51 8-bit microcontrollers
16K/32K, 512 OTP, I
2
C, watchdog timer
1999 Jul 23
6
PIN DESCRIPTIONS
PIN NO.
LCC
MNEMONIC
DIP
QFP
TYPE
NAME AND FUNCTION
V
SS
V
DD
20
40
22
44
16
38
I
I
Ground:
circuit ground potential.
Power Supply:
+5 V power supply pin during normal operation, Idle mode and
Power-down mode.
Port 0:
Port 0 is an open-drain, bidirectional I/O port. Port 0 pins that have 1s written to
them float and can be used as high-impedance inputs. Port 0 is also the multiplexed
low-order address and data bus during accesses to external program and data memory. In
this application, it uses strong internal pull-ups when emitting 1s.
Port 1:
Port 1 is an 8-bit bidirectional I/O port with internal pull-ups, except P1.6 and P1.7
which have open drain. Port 1 pins that have 1s written to them are pulled high by the
internal pull-ups and can be used as inputs. As inputs, port 1 pins that are externally pulled
low will source current because of the internal pull-ups. (See DC Electrical Characteristics:
I
). Port 1 can sink/source one TTL (4 LSTTL) inputs. Port 1 receives the low-order
address byte during program memory verification. Port 1 also serves alternate functions for
timer 2:
T2 (P1.0):
Timer/counter 2 external count input (following edge triggered).
T2EX (P1.1):
Timer/counter 2 trigger input.
SCL (P1.6):
I
2
C serial port clock line.
SDA (P1.7):
I
2
C serial port data line.
Port 2:
Port 2 is an 8-bit bidirectional I/O port with internal pull-ups. Port 2 pins that have
1s written to them are pulled high by the internal pull-ups and can be used as inputs. As
inputs, port 2 pins that are externally being pulled low will source current because of the
internal pull-ups. (See DC Electrical Characteristics: I
). Port 2 emits the high-order
address byte during fetches from external program memory and during accesses to
external data memory that use 16-bit addresses (MOVX @DPTR). In this application, it
uses strong internal pull-ups when emitting 1s. During accesses to external data memory
that use 8-bit addresses (MOV @Ri), port 2 emits the contents of the P2 special function
register.
Port 3:
Port 3 is an 8-bit bidirectional I/O port with internal pull-ups. Port 3 pins that have
1s written to them are pulled high by the internal pull-ups and can be used as inputs. As
inputs, port 3 pins that are externally being pulled low will source current because of the
pull-ups. (See DC Electrical Characteristics: I
IL
). Port 3 also serves the special features of
the SC80C51 family, as listed below:
RxD (P3.0):
Serial input port
TxD (P3.1):
Serial output port
INT0 (P3.2):
External interrupt
INT1 (P3.3):
External interrupt
T0 (P3.4):
Timer 0 external input
T1 (P3.5):
Timer 1 external input
WR (P3.6):
External data memory write strobe
RD (P3.7):
External data memory read strobe
Reset:
A high on this pin for two machine cycles while the oscillator is running, resets the
device. An internal diffused resistor to V
permits a power-on reset using only an external
capacitor to V
. After a watchdog timer overflow, this pin is pulled high while the internal
reset signal is active.
Address Latch Enable:
Output pulse for latching the low byte of the address during an
access to external memory. In normal operation, ALE is emitted at a constant rate of 1/6
the oscillator frequency, and can be used for external timing or clocking. Note that one ALE
pulse is skipped during each access to external data memory.
Program Store Enable:
The read strobe to external program memory. When the device is
executing code from the external program memory, PSEN is activated twice each machine
cycle, except that two PSEN activations are skipped during each access to external data
memory. PSEN is not activated during fetches from internal program memory.
External Access Enable:
EA must be externally held low during RESET to enable the
device to fetch code from external program memory locations 0000H to 7FFFH. If EA is
held high during RESET, the device executes from internal program memory unless the
program counter contains an address greater than 7FFFH. EA is don’t care after RESET.
Crystal 1:
Input to the inverting oscillator amplifier and input to the internal clock generator
circuits.
Crystal 2:
Output from the inverting oscillator amplifier.
P0.0–0.7
39–32
43–36
37–30
I/O
P1.0–P1.7
1–8
2–9
40–44
1–3
I/O
1
2
7
8
2
3
8
9
40
41
2
3
I
I
I/O
I/O
I/O
P2.0–P2.7
21–28
24–31
18–25
P3.0–P3.7
10–17
11,
13–19
5,
7–13
I/O
10
11
12
13
14
15
16
17
9
11
13
14
15
16
17
18
19
10
5
7
8
9
10
11
12
13
4
I
O
I
I
I
I
O
O
I/O
RST
ALE
30
33
27
I/O
PSEN
29
32
26
O
EA
31
35
29
I
XTAL1
19
21
15
I
XTAL2
18
20
14
O
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