參數(shù)資料
型號： 87C529
廠商： NXP Semiconductors N.V.
英文描述： 80C51 9-bit microcontrollers(80C51 9位微控制器)
中文描述： 80C51的8位微控制器（80C51的8位微控制器）
文件頁數(shù)： 11/26頁
文件大?。?/td> 266K
代理商： 87C529
Philips Semiconductors
Product specification
87C524/87C528
80C51 8-bit microcontrollers
16K/32K, 512 OTP, I
2
C, watchdog timer
1999 Jul 23
11
DC ELECTRICAL CHARACTERISTICS
T
amb
= 0
°
C to +70
°
C (V
DD
= 5 V
±
10%), –40
°
C to +85
°
C (V
DD
= 5 V
±
10%), V
SS
=0 V
TEST
LIMITS
SYMBOL
PARAMETER
PART TYPE
CONDITIONS
MIN
MAX
UNIT
V
IL
Input low voltage,
except EA, P1.6/SCL, P1.7/SDA
0
°
C to 70
°
C
–40
°
C to +85
°
C
–0.5
–0.5
0.2V
CC
–0.1
0.2V
CC
–0.15
V
V
V
IL1
Input low voltage to EA
0
°
C to 70
°
C
–40
°
C to +85
°
C
0
0
0.2V
CC
–0.3
0.2V
CC
–0.35
V
V
V
IL2
Input low voltage to P1.6/SCL, P1.7/SDA
5
–0.5
0.3 V
V
V
IH
Input high voltage,
except XTAL1, RST, P1.6/SCL, P1.7/SDA
0
°
C to 70
°
C
–40
°
C to +85
°
C
0.2V
CC
+0.9
0.2V
CC
+1.0
V
CC
+0.5
V
CC
+0.5
V
V
V
IH1
Input high voltage, XTAL1, RST
0
°
C to 70
°
C
–40
°
C to +85
°
C
0.7V
CC
0.7V
CC
V
CC
+0.5
V
CC
+0.5
V
V
V
IH2
V
OL
Input high voltage, P1.6/SCL, P1.7/SDA
5
3.0
6.0
V
Output low voltage, ports 1, 2, 3, except
P1.6/SCL, P1.7/SDA
1
Output low voltage, port 0, ALE, PSEN
1
Output low voltage, P1.6/SCL, P1.7/SDA
Output high voltage, ports 1, 2, 3
I
OL
= 1.6 mA
1
0.45
V
V
OL1
V
OL2
V
OH
I
OL
= 3.2 mA
1
I
OL
= 3.0 mA
1
I
OH
= –60
μ
A
I
OH
= –25
μ
A
I
OH
= –800
μ
A
I
OH
= –300
μ
A
V
IN
= 0.45 V
0.45
0.4
V
V
V
V
V
V
2.4
0.75V
CC
2.4
0.75V
CC
V
OH1
Output high voltage, Port 0 in external bus mode,
ALE, PSEN, RST
I
IL
Logical 0 input current, ports 1, 2, 3,
except P1.6/SCL, P1.7/SDA
0
°
C to 70
°
C
–40
°
C to +85
°
C
–50
–75
μ
A
μ
A
I
TL
Logical 1-to-0 transition current, ports 1, 2, 3,
except P1.6/SCL, P1.7/SDA
0
°
C to 70
°
C
–40
°
C to +85
°
C
See Note 3
–650
–750
μ
A
μ
A
I
IL1
Input leakage current, port 0
V
IN
= V
IL
or V
IH
±
10
μ
A
I
IL2
Input leakage current, P1.6/SCL, P1.7/SDA
0 V<Vi<6.0 V
0 V<V
CC
<6.0 V
±
10
μ
A
μ
A
I
CC
Power supply current:
See Note 4
Active mode @ 16 MHz
0
o
C to 70
o
C
–40
o
C to +85
o
C
0
o
C to 70
o
C
–40
o
C to +85
o
C
25
35
5
6
50
mA
Idle mode @ 16 MHz
mA
Power down mode
μ
A
k
pF
R
RST
C
IO
NOTES:
1. Capacitive loading on Port 0 and Port 2 may cause spurious noise pulses to be superimposed on the V
s of ALE and ports 1 and 3. The
noise is due to external bus capacitance discharging into the port and port 2 pins when these pins make 1-to-0 transactions during bus
operations. In the worst cases (capacitive loading > 100pF), the noise pulse on the ALE pin may exceed 0.8V. In such cases, it may be
desirable to qualify ALE with a Schmitt Trigger, or use an address latch with a Schmitt Trigger STROBE input. Under steady state
(non-transient) conditions, I
OL
must be externally limited as follows: 10 mA per port pin, port 0 total (all bits) 26 mA, ports 1, 2, and total each
(all bits) 15 mA.
2. Capacitive loading on Ports 0 and 2 may cause the V
OH
on ALE and PSEN to momentarily fall below the 0.9V
CC
specification when the
address bits are stabilizing.
3. Pins of ports 1, 2, and 3 source a transition current when they are being externally driven from 1 to 0. The transition current reaches its
maximum value when V
IN
is approximately 2 V.
4. See Figures 10 through 13 for I
CC
test conditions.
5. The input threshold voltage of P1.6 and P1.7 (SIO1) meets the I
2
C specification, so an input voltage below 1.5 V will be recognized as a
logic 0 while an input voltage above 3.0 V will be recognized as a logic 1.
Internal reset pull-down resistor
Pin Capacitance
50
300
10
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