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參數(shù)資料
| 型號： | 8742 |
| 廠商： | Intel Corp. |
| 英文描述： | 8742 Universal Peripheral Interface 8-Bit Slave Microcontroller(8742 通用外設(shè)接口8位從模式微控制器) |
| 中文描述： | 8742通用外圍設(shè)備接口的8位微控制器奴隸（8742通用外設(shè)接口8位從模式微控制器） |
| 文件頁數(shù)： | 4/12頁 |
| 文件大?。?/td> | 210K |
| 代理商： | 8742 |
8742
UPI-42 FEATURES
1.
Two Data Bus Buffers, one for input and one for
output. This allows a much cleaner Master/Slave
protocol.
290256–3
2.
8 Bits of Status
ST
7
ST
6
ST
5
ST
4
F
1
F
0
IBF OBF
D
7
D
6
D
5
D
4
D
3
D
2
D
1
D
0
ST
4
–ST
7
are user definable status bits. These
bits are defined by the ‘‘MOV STS, A’’ single byte,
single cycle instruction. Bits 4–7 of the acccumu-
lator are moved to bits 4–7 of the status register.
Bits 0–3 of the status register are not affected.
MOV STS, A
Op Code: 90H
1
0
0
1
0
0
0
0
D
7
D
0
3.
RD and WR are edge triggered. IBF, OBF, F
1
and
INT change internally after the trailing edge of RD
or WR.
290256–4
During the time that the host CPU is reading the
status register, the 8742 is prevented from updat-
ing this register or is ‘‘locked out’’.
4.
P
24
and P
25
are port pins or Buffer Flag pins
which can be used to interrupt a master proces-
sor. These pins default to port pins on Reset.
If the ‘‘EN FLAGS’’ instruction has been execut-
ed, P
24
becomes the OBF (Output Buffer Full) pin.
A ‘‘1’’ written to P
24
enables the OBF pin (the pin
outputs the OBF Status Bit). A ‘‘0’’ written to P
24
disables the OBF pin (the pin remains low). This
pin can be used to indicate that valid data is avail-
able from the UPI-41A (in Output Data Bus Buff-
er).
If ‘‘EN FLAGS’’ has been executed, P
25
becomes
the IBF (Input Buffer Full) pin. A ‘‘1’’ written to P
25
enables the IBF pin (the pin outputs the inverse of
the IBF Status Bit. A ‘‘0’’ written to P
25
disables
the IBF pin (the pin remains low). This pin can be
used to indicate that the UPI is ready for data.
290256–5
Data Bus Buffer Interrupt Capability
EN FLAGS
Op Code: 0F5H
1
1
1
1
0
1
0
1
D
7
D
0
5.
P
26
and P
27
are port pins or DMA handshake pins
for use with a DMA controller. These pins default
to port pins on Reset.
If the ‘‘EN DMA’’ instruction has been executed,
P
26
becomes the DRQ (DMA Request) pin. A ‘‘1’’
written to P
26
causes a DMA request (DRQ is acti-
vated).
DRQ
is
deactivated
DACK
#
WR, or execution of the ‘‘EN DMA’’ in-
struction.
by
DACK
#
RD,
If ‘‘EN DMA’’ has been executed, P
27
becomes
the DACK (DMA Acknowledge) pin. This pin acts
as a chip select input for the Data Bus Buffer reg-
isters during DMA transfers.
290256–6
DMA Handshake Capability
EN DMA
Op Code: 0E5H
1
1
1
0
0
1
0
1
D
7
D
0
6.
The RESET input on the 8742, includes a 2-stage
synchronizer to support reliable reset operation
for 12 MHz operation.
7.
When EA is enabled on the 8742, the program
counter is placed on Port 1 and the lower three
bits of Port 2 (MSB
e
P
22
, LSB
e
P
10
). On the
8742 this information is multiplexed with PORT
DATA (see port timing diagrams at end of this
data sheet).
4
4
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參數(shù)描述 |
|---|---|
| 8742 0601000 | 制造商:Belden Inc 功能描述:PAIRED CABLE, 3 PR, 22AWG SOLID, PVC INSULATED, INSTRUMENTATION/CONTROL CHROME 制造商:Belden Inc 功能描述:UNSHLD MULTIPR CABLE 3PR 1000FT 300V CHR, Reel Length (Imperial):1000ft, Reel Le 制造商:Belden Inc 功能描述:UNSHLD MULTIPR CABLE 3PR 1000FT 300V CHR, Reel Length (Imperial):1000ft, Reel Length (Metric):304.8m, LAN Category:-, No. of Pairs:3, Conductor Size AWG:22AWG, Jacket Color:Chrome, Jacket Material:PVC (Polyvinyl Chloride) , RoHS Compliant: Yes |
| 8742 060500 | 制造商:Belden Inc 功能描述:UNSHLD MULTIPR CABLE 3PR 500FT 300V CHR, Reel Length (Imperial):500ft, Reel Leng |
| 8742 0605000 | 功能描述:CBL 3COND 22AWG 制造商:belden inc. 系列:* 零件狀態(tài):在售 標(biāo)準(zhǔn)包裝:5,000 |
| 874208BKILF | 功能描述:時鐘驅(qū)動器及分配 RoHS:否 制造商:Micrel 乘法/除法因子:1:4 輸出類型:Differential 最大輸出頻率:4.2 GHz 電源電壓-最大: 電源電壓-最小:5 V 最大工作溫度:+ 85 C 封裝 / 箱體:SOIC-8 封裝:Reel |
| 874208BKILFT | 功能描述:時鐘驅(qū)動器及分配 RoHS:否 制造商:Micrel 乘法/除法因子:1:4 輸出類型:Differential 最大輸出頻率:4.2 GHz 電源電壓-最大: 電源電壓-最小:5 V 最大工作溫度:+ 85 C 封裝 / 箱體:SOIC-8 封裝:Reel |
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