參數(shù)資料
型號: 8742
廠商: Intel Corp.
英文描述: 8742 Universal Peripheral Interface 8-Bit Slave Microcontroller(8742 通用外設(shè)接口8位從模式微控制器)
中文描述: 8742通用外圍設(shè)備接口的8位微控制器奴隸(8742通用外設(shè)接口8位從模式微控制器)
文件頁數(shù): 3/12頁
文件大?。?/td> 210K
代理商: 8742
8742
Table 1. Pin Description
DIP
Pin
No.
Symbol
Type
Name and Function
TEST 0,
TEST 1
1
I
TEST INPUTS:
Input pins which can be directly tested using conditional branch
instructions.
FREQUENCY REFERENCE:
TEST 1 (T
1
) also functions as the event timer input (under
software control). TEST 0 (T
0
) is used during PROM programming and EPROM
verification.
39
XTAL 1,
XTAL 2
2
3
I
INPUTS:
Inputs for a crystal, LC or an external timing signal to determine the internal
oscillator frequency.
RESET
4
I
RESET:
Input used to reset status flip-flops and to set the program counter to zero.
RESET is also used during EPROM programming and verification.
SS
5
I
SINGLE STEP:
Single step input used in conjunction with the SYNC output to step the
program through each instruction (EPROM). This should be tied to
a
5V when not used.
CS
6
I
CHIP SELECT:
Chip select input used to select one UPI microcomputer out of several
connected to a common data bus.
EA
7
I
EXTERNAL ACCESS:
External access input which allows emulation, testing and EPROM
verification. This pin should be tied low if unused.
RD
8
I
READ:
I/O read input which enables the master CPU to read data and status words from
the OUTPUT DATA BUS BUFFER or status register.
A
0
9
I
COMMAND/DATA SELECT:
Address Input used by the master processor to indicate
whether byte transfer is data (A
0
e
0, F1 is reset) or command (A
0
e
1, F1 is set). A
0
e
0
during program and verify operations.
WR
10
I
WRITE:
I/O write input which enables the master CPU to write data and command words
to the UPI INPUT DATA BUS BUFFER.
SYNC
11
O
OUTPUT CLOCK:
Output signal which occurs once per UPI instruction cycle. SYNC can
be used as a strobe for external circuitry; it is also used to synchronize single step
operation.
(BUS)
D
0
–D
7
12–19
I/O
DATA BUS:
Three-state, bidirectional DATA BUS BUFFER lines used to interface the UPI
microcomputer to an 8-bit master system data bus.
P
10
–P
17
27–34
I/O
PORT 1:
8-bit, PORT 1 quasi-bidirectional I/O lines.
P
20
–P
27
21–24
35–38
I/O
PORT 2:
8-bit, PORT 2 quasi-bidirectional I/O lines. The lower 4 bits (P
20
–P
23
) interface
directly to the 8243 I/O expander device and contain address and data information during
PORT 4–7 access. The upper 4 bits (P
24
–P
27
) can be programmed to provide interrupt
Request and DMA Handshake capability. Software control can configure P
24
as Output
Buffer Full (OBF) interrupt, P
25
as Input Buffer Full (IBF) interrupt, P
26
as DMA Request
(DRQ), and P
27
as DMA ACKnowledge (DACK).
PROG
25
I/O
PROGRAM:
Multifunction pin used as the program pulse input during PROM programming.
During I/O expander access the PROG pin acts as an address/data strobe to the 8243.
This pin should be tied high if unused.
V
CC
40
POWER:
a
5V main power supply pin.
V
DD
26
POWER:
a
5V during normal operation.
a
21V during programming operation. Low power
standby supply pin.
V
SS
20
GROUND:
Circuit ground potential.
3
3
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