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參數資料
| 型號： | 87021AMIT |
| 廠商： | INTEGRATED DEVICE TECHNOLOGY INC |
| 元件分類： | 時鐘及定時 |
| 英文描述： | 87021 SERIES, LOW SKEW CLOCK DRIVER, 2 TRUE OUTPUT(S), 0 INVERTED OUTPUT(S), PDSO8 |
| 封裝： | 3.90 X 4.90 MM, 1.37 MM HEIGHT, MS-012, SOIC-8 |
| 文件頁數： | 14/14頁 |
| 文件大?。?/td> | 290K |
| 代理商： | 87021AMIT |
IDT / ICS LVCMOS CLOCK GENERATOR
9
ICS87021AMI REV. B AUGUST 26, 2008
ICS87021I
÷1/÷2 DIFFERENTIAL-TO-LVCMOS/LVTTL CLOCK GENERATOR
FIGURE 2C. HIPERCLOCKS CLK/nCLK INPUT DRIVEN BY
3.3V LVPECL DRIVER
FIGURE 2B. HIPERCLOCKS CLK/nCLK INPUT DRIVEN BY
3.3V LVPECL DRIVER
FIGURE 2D. HIPERCLOCKS CLK/nCLK INPUT DRIVEN BY
3.3V LVDS DRIVER
3.3V
R1
50
R3
50
Zo = 50 Ohm
LVPECL
Zo = 50 Ohm
HiPerClockS
CLK
nCLK
3.3V
Input
R2
50
Zo = 50 Ohm
Input
HiPerClockS
CLK
nCLK
3.3V
R3
125
R2
84
Zo = 50 Ohm
3.3V
R4
125
LVPECL
R1
84
3.3V
DIFFERENTIAL CLOCK INPUT INTERFACE
The CLK /nCLK accepts LVDS, LVPECL, LVHSTL, SSTL, HCSL
and other differential signals. Both signals must meet the V
PP and
V
CMR input requirements. Figures 2A to 2E show interface examples
for the HiPerClockS CLK/nCLK input driven by the most common
driver types. The input interfaces suggested here are examples
FIGURE 2A. HIPERCLOCKS CLK/nCLK INPUT DRIVEN BY
IDT HIPERCLOCKS LVHSTL DRIVER
only. Please consult with the vendor of the driver component to
confirm the driver termination requirements. For example in
Figure
2A, the input termination applies for IDT HiPerClockS LVHSTL
drivers. If you are using an LVHSTL driver from another vendor,
use their termination recommendation.
1.8V
R2
50
Input
LVHSTL Driver
ICS
HiPerClockS
R1
50
LVHSTL
3.3V
Zo = 50 Ohm
HiPerClockS
CLK
nCLK
FIGURE 2E. HIPERCLOCKS CLK/nCLK INPUT DRIVEN BY
3.3V LVPECL DRIVER WITH AC COUPLE
Zo = 50 Ohm
R3
125
HiPerClockS
CLK
nCLK
3.3V
R5
100 - 200
3.3V
R2
84
3.3V
R6
100 - 200
Input
R5,R6 locate near the driver pin.
Zo = 50 Ohm
R1
84
R4
125
C2
LVPECL
C1
Zo = 50 Ohm
R1
100
3.3V
LVDS_Driv er
Zo = 50 Ohm
Receiv er
CLK
nCLK
3.3V
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