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參數(shù)資料
| 型號： | 87021AMIT |
| 廠商： | INTEGRATED DEVICE TECHNOLOGY INC |
| 元件分類： | 時(shí)鐘及定時(shí) |
| 英文描述： | 87021 SERIES, LOW SKEW CLOCK DRIVER, 2 TRUE OUTPUT(S), 0 INVERTED OUTPUT(S), PDSO8 |
| 封裝： | 3.90 X 4.90 MM, 1.37 MM HEIGHT, MS-012, SOIC-8 |
| 文件頁數(shù)： | 13/14頁 |
| 文件大?。?/td> | 290K |
| 代理商： | 87021AMIT |
IDT / ICS LVCMOS CLOCK GENERATOR
8
ICS87021AMI REV. B AUGUST 26, 2008
ICS87021I
÷1/÷2 DIFFERENTIAL-TO-LVCMOS/LVTTL CLOCK GENERATOR
APPLICATION INFORMATION
Figure 1 shows how the differential input can be wired to accept
single ended levels. The reference voltage V_REF = V
DD
/2 is
generated by the bias resistors R1, R2 and C1. This bias circuit
should be located as close as possible to the input pin. The ratio
FIGURE 1. SINGLE ENDED SIGNAL DRIVING DIFFERENTIAL INPUT
WIRING THE DIFFERENTIAL INPUT TO ACCEPT SINGLE ENDED LEVELS
of R1 and R2 might need to be adjusted to position the V_REF in
the center of the input voltage swing. For example, if the input
clock swing is only 2.5V and V
DD
= 3.3V, V_REF should be 1.25V
and R2/R1 = 0.609.
V_REF
R1
1K
C1
0.1u
R2
1K
Single Ended Clock Input
CLK
nCLK
VDD
INPUTS:
LVCMOS CONTROL PINS
All control pins have internal pullups or pulldowns; additional
resistance is not required but can be added for additional
protection. A 1k
Ω resistor can be used.
RECOMMENDATIONS FOR UNUSED INPUT AND OUTPUT PINS
OUTPUTS:
LVCMOS OUTPUTS
All unused LVCMOS output can be left floating. There should be
no trace attached.
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