參數(shù)資料
型號(hào): 85304AG-01
廠商: INTEGRATED DEVICE TECHNOLOGY INC
元件分類: 時(shí)鐘及定時(shí)
英文描述: 85304 SERIES, LOW SKEW CLOCK DRIVER, 5 TRUE OUTPUT(S), 0 INVERTED OUTPUT(S), PDSO20
封裝: 6.50 X 4.40 MM, 0.92 MM PITCH, MO-153, TSSOP-20
文件頁(yè)數(shù): 9/15頁(yè)
文件大?。?/td> 760K
代理商: 85304AG-01
ICS85304-01
LOW SKEW, 1-TO-5 DIFFERENTIAL-TO- 3.3V LVPECL FANOUT BUFFER
IDT / ICS 3.3V LVPECL FANOUT BUFFER
3
ICS85304AG-01 REV. E JULY 8, 2008
Function Tables
Table 3A. Control Input Function Table
After CLK_EN switches, the clock outputs are disabled or enabled following a rising and falling input clock edge as shown in Figure 1.
In the active mode, the state of the outputs are a function of the CLKx/nCLKx inputs as described in Table 3B.
Figure 1. CLK_EN Timing Diagram
Table 3B. Clock Input Function Table
NOTE 1: Please refer to the Application Information section, Wiring the Differential Input to Accept Single-Ended Levels.
Inputs
Outputs
CLK_EN
CLK_SEL
Selected Source
Q0:Q4
nQ0:nQ4
0
CLK0, nCLK0
Disabled; LOW
Disabled; HIGH
0
1
CLK1, nCLK1
Disabled; LOW
Disabled; HIGH
1
0
CLK0, nCLK0
Enabled
1
CLK1, nCLK1
Enabled
Inputs
Outputs
Input to Output Mode
Polarity
CLK0 or CLK1
nCLK0 or nCLK1
Q[0:4]
nQ[0:4]
0
1
LOW
HIGH
Differential to Differential
Non-Inverting
1
0
HIGH
LOW
Differential to Differential
Non-Inverting
0
Biased; NOTE 1
LOW
HIGH
Single-Ended to Differential
Non-Inverting
1
Biased; NOTE 1
HIGH
LOW
Single-Ended to Differential
Non-Inverting
Biased; NOTE 1
0
HIGH
LOW
Single-Ended to Differential
Inverting
Biased; NOTE 1
1
LOW
HIGH
Single-Ended to Differential
Inverting
Enabled
Disabled
CLK[0:1]
CLK_EN
nCLK[0:1]
Q[0:4]
nQ[0:4]
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85304AGI-01LFT 制造商:Integrated Device Technology Inc 功能描述:NETCOM - Bulk