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| 型號： | 840021AKILF |
| 廠商： | INTEGRATED DEVICE TECHNOLOGY INC |
| 元件分類： | 時鐘產(chǎn)生/分配 |
| 英文描述： | 125 MHz, OTHER CLOCK GENERATOR, QCC16 |
| 封裝： | 3 X 3 MM, 0.925 MM HEIGHT, ROHS COMPLIANT, MO-220EED-2, VFQFN-16 |
| 文件頁數(shù)： | 16/16頁 |
| 文件大?。?/td> | 767K |
| 代理商： | 840021AKILF |
ICS840021AGI REVISION C JANUARY 27, 2010
9
2010 Integrated Device Technology, Inc.
ICS840021I Data Sheet
FEMTOCLOCK CRYSTAL-TO-LVCMOS/LVTTL CLOCK GENERATOR
LVCMOS to XTAL Interface
The XTAL_IN input can accept a single-ended LVCMOS signal
through an AC coupling capacitor. A general interface diagram is
shown in Figure 3. The XTAL_OUT pin can be left floating. The input
edge rate can be as slow as 10ns. For LVCMOS signals, it is
recommended that the amplitude be reduced from full swing to half
swing in order to prevent signal interference with the power rail and
to reduce noise. This configuration requires that the output
impedance of the driver (Ro) plus the series resistance (Rs) equals
the transmission line impedance. In addition, matched termination at
the crystal input will attenuate the signal in half. This can be done in
one of two ways. First, R1 and R2 in parallel should equal the
transmission line impedance. For most 50
applications, R1 and R2
can be 100
. This can also be accomplished by removing R1 and
making R2 50
.
Figure 3. General Diagram for LVCMOS Driver to XTAL Input Interface
XTAL_IN
XTAL_OUT
Ro
Rs
Zo = Ro + Rs
50
0.1f
R1
R2
VDD
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