參數(shù)資料
型號(hào)： 82845MP
廠商： INTEL CORP
元件分類： 外設(shè)及接口
英文描述： Intel 845 Family Chipset-Mobile 82845MP/82845MZ Chipset Memory Controller Hub Mobile (MCH-M)
中文描述： MULTIFUNCTION PERIPHERAL, PBGA593
封裝： 37.50 X 37.50 MM, FCBGA-593
文件頁數(shù)： 94/157頁
文件大?。?/td> 1407K
代理商： 82845MP
Intel
82845MP/82845MZ Chipset-Mobile (MCH-M)
94
Datasheet
250687-002
R
3.8.14.
IOBASE1 – I/O Base Address Register – Device #1
Address Offset:
Default Value:
Access:
Size:
1Ch
F0h
Read/Write, Read Only
8 bits
This register controls the hosts to AGP I/O access routing based on the following formula:
IO_BASE=< address =<IO_LIMIT
Only the upper 4 bits are programmable. For the purpose of address decode address bits A[11:0] are
treated as 0. Thus the bottom of the defined I/O address range will be aligned to a 4-KB boundary.
Bit
Description
7:4
I/O Address Base.
Corresponds to A[15:12] of the I/O address. Default=Fh
3:0
Reserved
3.8.15.
IOLIMIT1 – I/O Limit Address Register – Device #1
Address Offset:
Default Value:
Access:
Size:
1Dh
00h
Read/Write, Read Only
8 bits
This register controls the hosts to AGP I/O access routing based on the following formula:
IO_BASE=< address =<IO_LIMIT
Only the upper 4 bits are programmable. For the purpose of address decode address bits A[11:0] are
assumed to be FFFh. Thus, the top of the defined I/O address range will be at the top of a 4-KB aligned
address block.
Bit
Description
7:4
I/O Address Limit.
Corresponds to A[15:12] of the I/O address. Default=0h
3:0
Reserved
(Only 16-bit addressing supported)
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82845MX 制造商:INTEL 制造商全稱:Intel Corporation 功能描述:Intel 845 Family Chipset-Mobile 82845MP/82845MZ Chipset Memory Controller Hub Mobile (MCH-M)
82845MZ 制造商:INTEL 制造商全稱:Intel Corporation 功能描述:Intel 845 Family Chipset-Mobile 82845MP/82845MZ Chipset Memory Controller Hub Mobile (MCH-M)
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