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參數(shù)資料
| 型號： | 82572EI |
| 廠商： | INTEL CORP |
| 元件分類： | 微控制器/微處理器 |
| 英文描述： | Gigabit Ethernet Controller |
| 中文描述： | 1 CHANNEL(S), 1000M bps, LOCAL AREA NETWORK CONTROLLER, BGA256 |
| 封裝： | 17 X 17 MM, FC-BGA-256 |
| 文件頁數(shù)： | 15/58頁 |
| 文件大?。?/td> | 318K |
| 代理商： | 82572EI |
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Product Datasheet
9
82571EB/82572EI Gigabit Ethernet Controller
3.0
Signal Descriptions
Note:
The targeted signal names are subject to change without notice. Verify with your local Intel sales
office that you have the latest information before finalizing a design.
3.1
Signal Type Definitions
The signals of the 82571EB/82572EI controller are electrically defined as follows:
3.2
PCI Express Interface
Name
Definition
I
Input.
Standard input only digital signal.
O
Output.
Standard output only digital signal.
TS
Tri-state.
Bi-directional three-state digital input/output signal.
OD
Open Drain.
Wired-OR with other agents.
The signaling agent asserts the OD signal, but the signal is returned to the inactive state by a weak pull-
up resistor. The pull-up resistor may require two or three clock periods to fully restore the signal to the
de-asserted state.
A
Analog.
PCI Express*, SERDES, or, PHY analog signal.
A(I)
Analog-Input.
Standard input only analog signal.
A(O)
Analog-Output.
Standard output only analog signal.
P
Power.
Power connection, voltage reference, or other reference connection.
Symbol
Type
Name and Function
PERn[3:0]
PERp[3:0]
A(I)
High Speed Serial Receive Data.
These signals connect to corresponding PETn and
PETp signals on a system motherboard or a PCI Express connector. Series AC coupling
capacitors are required at the transmitter end. The PCI Express differential inputs are
clocked at 2.5 Gb/s.
PETn[3:0]
PETp[3:0]
A(O)
High Speed Serial Transmit Data.
These signals connect to corresponding PERn and
PERp signals on a system motherboard or a PCI Express connector. Series AC coupling
capacitors are required at the 82571EB/82572EI controller end. The PCI Express
differential outputs are clocked at 2.5 Gb/s.
PE_RCOMPp
PE_RCOMPn
P
High Speed Serial Impedance Compensation.
Connect the recommended resistor value
across these balls. Refer to the 82571EB/82572EI Design Guide for the recommended
value.
PE_CLKp
PE_CLKn
I
100 MHz Differential Clock for the PCI Express Interface.
The reference clock is
furnished by the system and has a 300 ppm frequency tolerance.
PE_RSTn
I
PCI Express Reset.
When the signal is low, all PCI Express functions are held in reset.
When the signal is high, it denotes that main power is available to the 82571EB/82572EI
controller and the reference clock is running.
In systems with a PCI Express add-in card, this signal routes to the connector.
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