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參數(shù)資料
| 型號(hào)： | 82503 |
| 廠商： | Intel Corp. |
| 英文描述： | DUAL SERIAL TRANSCEIVER (DST) |
| 中文描述： | 雙串行收發(fā)器（DST）的 |
| 文件頁(yè)數(shù)： | 21/45頁(yè) |
| 文件大小： | 562K |
| 代理商： | 82503 |
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82503
DC CHARACTERISTICS
(T
C
e
0
§
C to
a
85
§
C, V
CC
e
5V
g
5%, V
CCA
e
5V
g
5%) (Continued)
Symbol
Parameter
Min
Max
Units
Test Conditions
I
OSC
(AUI)
AUI Output Short Circuit Current
g
150
mA
Short Circuit to V
CC
or GND
V
U
(AUI)
Output Differential Undershoot
b
100
mV
V
ODI
(AUI) Differential Idle Voltage
(11)
g
40
mV
I
CC
(HOT)
Power Supply Current
(12)
65
mA
APORT
e
1
I
CC
Power Supply Current
75
mA
APORT
e
1
I
CC
Power Supply Current
60
mA
APORT
e
0
I
CCSB
Standby Supply Current
(13)
1
mA
Low Power Mode, 20
m
A Typical
PD (HOT)
Power Dissipation
(12)
0.38
W
APORT
e
1, Continuous Transmission
on AUI
PD
Power Dissipation
0.40
W
APORT
e
1, Continuous Transmission
on AUI
PD
SB
Standby Power Dissipation
(13)
5.25
mW
Low Power Mode, 105
m
W Typical
C
IN(14)
Input Capacitance
10
pF
at f
e
1 MHz
NOTES:
11. Measured 8.0
m
s after last positive transition of data packet.
12. I
CC
HOT measurements made at T
C
e a
85
§
C. Additionally, TRMT, TRMT, TDH, TDH, TDL, TDL are loaded with 20 pF
and load resistors removed.
13. Pins CS0 and CS1 connected to V
or V
SS
through a 2.5 k
X
(or less) resistor. I
CCSB
is typically at 20
m
A after 30s
from power down assertionDnot tested.
14. Characterized, not tested. (Controller interface and mode pins only.)
AC TIMING CHARACTERISTICS
290421–8
Figure 9. MOS Input Voltage Levels
(TTL Compatible) for Timing Measurements
(TxD, RTS, TPE/AUI, APORT, APOL/XSQ,
LID, LPBK, JABD, TEST, and RESET).
290421–9
Figure 10. Voltage Levels for MOS Level
Output Timing Measurements
(TxC, RxD, RxC, CRS, and CDT).
290421–10
Figure 11. Voltage Levels for Differential Input
Timing Measurements (RCV and CLSN Pairs).
290421–11
Figure 12. Voltage Levels for TRMT Pair
Output Timing Measurements.
21
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