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參數(shù)資料
| 型號： | 82503 |
| 廠商： | Intel Corp. |
| 英文描述： | DUAL SERIAL TRANSCEIVER (DST) |
| 中文描述： | 雙串行收發(fā)器（DST）的 |
| 文件頁數(shù)： | 20/45頁 |
| 文件大?。?/td> | 562K |
| 代理商： | 82503 |
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82503
7.0
ELECTRICAL SPECIFICATIONS
AND TIMINGS
ABSOLUTE MAXIMUM RATINGS
Case Temperature Under Biasààààààà0
§
C to
a
85
§
C
Storage Temperature àààààààààà
b
65
§
C to
a
140
§
C
All Output and Supply Voltages ààààà
b
0.5V to
a
7V
All Input Voltages ààààààààààààà
b
1.0V to
a
6.0V
(1)
NOTICE: This is a production data sheet. The specifi-
cations are subject to change without notice.
*
WARNING: Stressing the device beyond the ‘‘Absolute
Maximum Ratings’’ may cause permanent damage.
These are stress ratings only. Operation beyond the
‘‘Operating Conditions’’ is not recommended and ex-
tended exposure beyond the ‘‘Operating Conditions’’
may affect device reliability.
DC CHARACTERISTICS
(T
C
e
0
§
C to
a
85
§
C, V
CC
e
5V
g
5%, V
CCA
e
5V
g
5%)
Symbol
Parameter
Min
Max
Units
Test Conditions
V
IL
(TTL)
(2)
Input Low Voltage
b
0.3
0.8
V
V
IH
(TTL)
(2)
Input High Voltage
2.0
V
CC
V
I
LI(2)
Input Leakage Current
g
10
m
A
0.0V
s
V
I
s
V
CC
, RESET
e
1
V
OL
(MOS)
(3)
Output Low Voltage
0.45
V
I
OL
e
4 mA
V
OH
(MOS)
Output High Voltage
3.9
V
I
OH
e b
500
m
A
V
OL
(LED)
(4)
Output Low Voltage
0.45
V
I
OL
e
10 mA
V
OH
(LED)
Output High Voltage
3.9
V
I
OH
e b
500
m
A
I
LP
Leakage Current, Low
Power Mode
(5)
g
10
m
A
0.0V
s
V
I
s
V
CC
R
DIFF
Input Differential Resistance
(6)
10
k
X
dc
V
IDF
(TPE)
(7)
Input Differential Accept
Input Differential Reject
Input Differential Accept (XSQ)
Input Differential Reject (XSQ)
g
0.500
g
3.1
g
0.300
g
3.1
g
0.180
V
P
V
P
V
P
V
P
5 MHz
s
f
s
10 MHz
(Note 8)
R
S
(TPE)
(8)
Output Source Resistance
6
13
X
l
I
LOAD
l
e
25 mA
V
IDF
(AUI)
(9)
Input Differential Accept
Input Differential Reject
g
0.300
g
1.5
g
0.160
V
P
V
P
V
ODF
(AUI)
(10)
Output Differential Voltage
g
0.450
g
1.20
V
NOTES:
1. The voltage levels for RCV, CLSN, and RD pairs are
b
0.75V to
a
8.5V.
2. TTL Input Pins: TxD, RTS, TPE/AUI, APORT, APOL/XSQ, LID, CS0, CS1, LPBK, JABD, TEST, RESET.
3. MOS Output Pins: TxC, RxD, RxC, CRS, CDT.
4. LED Pins: TPE/AUI, TxLED, RxLED, COLED, POLED, LILED. V
OL
measured 10 ns after falling edge of TxC.
5. Pins: APORT, APOL/XSQ, LID, TPE/AUI, POLED, LILED, RTS, LPBK, RxD, TxD, CRS,
CDT, CS0, CS1, JABD, TEST, and RESET.
6. Pins: RD to RD, RCV to RCV, and CLSN to CLSN.
7. TPE Input Pins: RD, and RD. See Section 3.3.4 and Section 3.3.5.
8. Typically it is
b
4.5 dB below normal squelch level.
9. TPE Output Pins: TDH, TDH, TDL, and TDL. R
S
measures V
CC
or V
SS
to Pin.
10. AUI Input Pins: RCV, and CLSN pairs.
11. AUI Output Pins: TRMT pair.
20
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