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Intel 450NX PCIset
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CONTENTS
Chapter 1
Introduction ......................................................................................................................................... 1-1
1.1
Overview ..................................................................................................................................................... 1-1
1.2
Intel
450NX PCIset Components .............................................................................................................. 1-2
1.3
Intel
450NX PCIset Feature Summary ...................................................................................................... 1-3
1.4
Packaging & Power ..................................................................................................................................... 1-4
Chapter 2
Signal Descriptions ............................................................................................................................ 2-1
2.1
Conventions ................................................................................................................................................ 2-1
2.2
Summary ..................................................................................................................................................... 2-2
2.2.1
Signal Summary, By Component .................................................................................................. 2-2
2.2.1.1
MIOC Signal List .......................................................................................................... 2-3
2.2.1.2
PXB Signal List ............................................................................................................ 2-4
2.2.1.3
RCG Signal List ........................................................................................................... 2-5
2.2.1.4
MUX Signal List ........................................................................................................... 2-5
2.3
System Interface ......................................................................................................................................... 2-6
2.3.1
System / MIOC Interface ............................................................................................................... 2-6
2.3.2
Third-Party Agent / MIOC Interface .............................................................................................. 2-8
2.4
PCI Interface ............................................................................................................................................... 2-8
2.4.1
Primary Bus .................................................................................................................................. 2-8
2.4.2
64-bit Access Support ................................................................................................................. 2-10
2.4.3
Internal vs. External Arbitration ................................................................................................... 2-10
2.4.4
PIIX4E Interface .......................................................................................................................... 2-11
2.5
Memory Subsystem Interface .................................................................................................................... 2-12
2.5.1
External Interface ........................................................................................................................ 2-12
2.5.2
Internal Interface ......................................................................................................................... 2-14
2.5.2.1
RCG / DRAM Interface .............................................................................................. 2-14
2.5.2.2
DRAM / MUX Interface .............................................................................................. 2-15
2.5.2.3
RCG / MUX Interface ................................................................................................. 2-15
2.6
Expander Interface .................................................................................................................................... 2-15
2.7
Common Support Signals ......................................................................................................................... 2-17
2.7.1
JTAG Interface ............................................................................................................................ 2-17
2.7.2
Reference Signals ....................................................................................................................... 2-17
2.8
Component-Specific Support Signals ........................................................................................................ 2-18
2.8.1
MIOC ........................................................................................................................................... 2-18
2.8.2
PXB ............................................................................................................................................ 2-19
2.8.3
RCG ............................................................................................................................................ 2-19
2.8.4
MUX ............................................................................................................................................ 2-19
Chapter 3
Register Descriptions ......................................................................................................................... 3-1
3.1
Access Restrictions ..................................................................................................................................... 3-1
3.2
I/O Mapped Registers ................................................................................................................................. 3-1
3.2.1
CONFIG_ADDRESS: Configuration Address Register ............................................................... 3-1