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參數(shù)資料
| 型號(hào)： | 7P008CLF1101C20 |
| 廠商： | WHITE ELECTRONIC DESIGNS CORP |
| 元件分類： | PROM |
| 英文描述： | 4M X 16 FLASH 3V PROM CARD, 200 ns, XMA50 |
| 封裝： | CARD-50 |
| 文件頁數(shù)： | 5/11頁 |
| 文件大?。?/td> | 151K |
| 代理商： | 7P008CLF1101C20 |
3
White Electronic Designs Corporation (508) 485-4000 www.whiteedc.com
White Electronic Designs
Compact Linear Flash
Memory Card - CLF11 Series
For information regarding modes of operation, commands, and programming details
for the memory components, please consult the Intel StrataFlash J3 data sheet.
http://developer.intel.com/design/flcomp/datashts/290667.htm
Writing commands to the CUI enables reading of device data, query, identifier codes, inspection and clearing of the
status register, and, when VPEN = VPENH, block erasure, program, and lock-bit configuration.
The Block Erase command requires appropriate command data and an address within the block to be erased. The
Byte/Word Program command requires the command and address of the location to be written. Set Block Lock-Bit
commands require the command and block within the device to be locked. The Clear Block Lock-Bits command
requires the command and address within the device.
The CUI does not occupy an addressable memory location. It is written when the device is enabled and WE is
active. The address and data needed to execute a command are latched on the rising edge of WE or the first edge
of CE1 or CE2 that disables the card. Standard microprocessor write timings are used.
PINOUT
Pin
Signal name
I/O
Function
Active
1
GND
Ground
2DQ3
I/O
Data bit 3
3DQ4
I/O
Data bit 4
4DQ5
I/O
Data bit 5
5DQ6
I/O
Data bit 6
6DQ7
I/O
Data bit 7
7CE1
I
Card enable 1
LOW
8A11
I
Address bit 10
9
OE
I
Output enable
LOW
10
A10
I
Address bit 11
11
A9
I
Address bit 9
12
A8
I
Address bit 8
13
VCC
Supply Voltage
14
A7
I
Address bit 7
15
A6
I
Address bit 6
16
A5
I
Address bit 5
17
A4
I
Address bit 4
18
A3
I
Address bit 3
19
A2
I
Address bit 2
20
A1
I
Address bit 1
21
DQ0
I/O
Data bit 0
22
DQ1
I/O
Data bit 1
23
DQ2
I/O
Data bit 2
24
A12
I
Address bit 12
25
CD2
O
Card Detect 2
LOW
Pin
Signal name
I/O
Function
Active
26
CD1
O
Card Detect 1
LOW
27
DQ11
I/O
Data bit 11
28
DQ12
I/O
Data bit 12
29
DQ13
I/O
Data bit 13
30
DQ14
I/O
Data bit 14
31
DQ15
I
Data bit 15
32
CE2
I
Card enable 2
LOW
33
A22
I
Address bit 22
34
A21
I
Address bit 21
35
A20
I
Address bit 20
36
WE
I
Write Enable
LOW
37
A24
I
Address bit 24
38
VCC
Supply Voltage
39
A19
I
Address bit 19
40
A18
I
Address bit 18
41
A23
I
Address bit 23
42
A17
I
Address bit 17
43
A16
I
Address bit 16
44
A15
I
Address bit 15
45
A14
I
Address bit 14
46
A13
I
Address bit 13
47
DQ8
I/O
Data bit 8
48
DQ9
I/O
Data bit 9
49
DQ10
O
Data bit 10
50
GND
Ground
LOW
Notes:
16 bit operation; using 2 independent Low and High byte enables: single byte access ability
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