參數(shù)資料
型號: 79RC32K438233BB
廠商: INTEGRATED DEVICE TECHNOLOGY INC
元件分類: 微控制器/微處理器
英文描述: IDTTM InterpriseTM Integrated Communications Processor
中文描述: 32-BIT, 233 MHz, RISC PROCESSOR, PBGA416
封裝: 27 X 27 MM, PLASTIC, BGA-416
文件頁數(shù): 25/59頁
文件大?。?/td> 644K
代理商: 79RC32K438233BB
25 of 59
May 25, 2004
IDT 79RC32438
Figure 8 Memory and Peripheral Bus AC Timing Waveform — Read Access
DMAREQN[1:0]
Tpw_8n
2
None
2(ICLK)
2(ICLK)
2(ICLK)
2(ICLK)
ns
See Figures 10
and 11.
DMADONEN[1:0]
Tsu_8o
EXTCLK rising
6.0
6.0
6.0
6.0
ns
Thld_8o
1.0
1.0
1.0
1.0
ns
DMAFINN[1:0]
Tdo_8p
EXTCLK rising
1.5
6.0
1.5
6.0
1.5
6.0
1.5
6.0
ns
CPU, INST
Tdo_8m
EXTCLK rising
2.0
10.0
2.0
10.0
2.0
10.0
2.0
10.0
ns
See Figures 8
and 9.
1.
The RC32438 provides bus turnaround cycles to prevent bus contention when going from a read to write, write to read, and during external bus ownership. For example, there are
no cycles where an external device and the RC32438 are both driving. See Chapter 6, Device Controller, in the RC32438 User Reference Manual.
2.
The values for this symbol were determined by calculation, not by testing.
3.
The frequency of EXTCLK is programmable. See the External Clock Divider description in Table 3 of this data sheet.
4.
WAITACKN must meet the setup and hold times if it is synchronous or the minimum pulse width if it is asynchronous.
Signal
Symbol
Reference
Edge
200MHz
233MHz
266MHz
300MHz
Unit
Conditions
Timing
Diagram
Reference
Min
Max
Min
Max
Min
Max
Min
Max
Table 8 Memory and Peripheral Bus AC Timing Characteristics (Part 3 of 3)
Addr[21:0]
Addr[25:22]
1111
Data
Tdo_8f
Tdo_8f
Tdo_8e
Tdo_8e
Tzd_8c
Tdz_8c
Tdo_8k
Tdo_8k
Tdo_8i
Tdo_8i
Tdo_8b
Tdo_8a
Thld_8c
Tsu_8c
EXTCLK
MADDR[21:0]
MADDR[25:22]
RWN
CSN[5:0]
BWEN[1:0]
OEN
MDATA[15:0]
BDIRN
BOEN
WAITACKN
RC32438
samples
read data
Tper_8d
Thigh_8d
Tlow_8d
Tdo_8m
Tdo_8m
CPU,
INST
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