參數(shù)資料
型號(hào): 79RC32K438233BBI
廠商: INTEGRATED DEVICE TECHNOLOGY INC
元件分類: 微控制器/微處理器
英文描述: IDTTM InterpriseTM Integrated Communications Processor
中文描述: 32-BIT, 233 MHz, RISC PROCESSOR, PBGA416
封裝: 27 X 27 MM, PLASTIC, BGA-416
文件頁數(shù): 1/59頁
文件大?。?/td> 644K
代理商: 79RC32K438233BBI
1 of 59
May 25, 2004
2004 Integrated Device Technology, Inc.
DSC 6148
IDT and the IDT logo are registered trademarks of Integrated Device Technology, Inc.
Features
32-bit CPU Core
MIPS32 instruction set
Cache Sizes: 16KB instruction and data caches, 4-Way set
associative, cache line locking, non-blocking prefetches
16 dual-entry JTLB with variable page sizes
3-entry instruction TLB
3-entry data TLB
Max issue rate of one 32x16 multiply per clock
Max issue rate of one 32x32 multiply every other clock
CPU control with start, stop and single stepping
Software breakpoints support
Hardware breakpoints on virtual addresses
Enhanced JTAG and ICE Interface that is compatible with v2.5
of the EJTAG Specification
DDR Memory Controller
Supports up to 2GB of DDR SDRAM
2 chip selects (each chip select supports 4 internal DDR
banks)
Supports 16-bit or 32-bit data bus width using 8, 16, or 32-bit
devices
Supports 64Mb, 128Mb, 256Mb, 512Mb, and 1Gb DDR
SDRAM devices
Data bus multiplexing support allows interfacing to standard
DDR DIMMs and SODIMMs
Automatic refresh generation
Memory and Peripheral Device Controller
Provides “glueless” interface to standard SRAM, Flash, ROM,
dual-port memory, and peripheral devices
Demultiplexed address and data buses: 16-bit data bus, 26-bit
address bus, 6 chip selects, supports alternate bus masters,
control for external data bus buffers
Supports 8-bit and 16-bit width devices
Automatic byte gathering and scattering
Flexible protocol configuration parameters: programmable
number of wait states (0 to 63), programmable postread/post-
write delay (0 to 31), supports external wait state generation,
supports Intel and Motorola style peripherals
Write protect capability per chip select
Programmable bus transaction timer generates warm reset
when counter expires
Supports up to 64 MB of memory per chip select
Counter/Timers
Three general purpose 32-bit counter timers
PCI Interface
32-bit PCI revision 2.2 compliant (3.3V only)
Supports host or satellite operation in both master and target
modes
Support for synchronous and asynchronous operation
PCI clock supports frequencies from 16 MHz to 66 MHz
PCI arbiter in Host mode: supports 6 external masters, fixed
priority or round robin arbitration
I
2
O “l(fā)ike” PCI Messaging Unit
Block Diagram
EJTAG
MMU
D. Cache
I. Cache
MIPS-32
CPU Core
ICE
Interrupt
Controller
3 Counter
Timers
DMA
Controller
Arbiter
DDR
DDR &
Device
Controllers
2 UARTS
(16550)
GPIO
Interface
PCI
Master/Target
Interface
Memory &
Peripheral Bus
Ch. 1 Ch. 2
Serial Channels
GPIO Pins
PCI Bus
Controller
Controller
SPI
I
2
C
SPI Bus
I
2
C Bus
:
:
10/100
Interfaces
2 Ethernet
MII
MII
IPBus
TM
PCI Arbiter
(Host Mode)
On-Chip
Memory
79RC32438
IDT
TM
Interprise
TM
Integrated
Communications Processor
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