參數(shù)資料
型號： 79RC32K438-300BB
廠商： Integrated Device Technology, Inc.
英文描述： IDTTM InterpriseTM Integrated Communications Processor
中文描述： IDTTM InterpriseTM集成通信處理器
文件頁數(shù)： 21/59頁
文件大?。?/td> 644K
代理商： 79RC32K438-300BB
21 of 59
May 25, 2004
IDT 79RC32438
Figure 5 Warm Reset AC Timing Waveform
Signal
Symbol
1
1.
In the DDR data sheet:
Tskew_7g = t
DQSQ;
Tdo_7k = t
DH
, t
DS;
Tdo_7l = t
DH
, t
DS;
Tac = t
AC;
Tdo_7m = t
IH
, t
IS.
2.
Meets DDR timing requirements for DDR 266 SDRAMs with 400 ps remaining margin to compensate for PCB propagation mismatches, which is adequate to guarantee functional
timing, provided the RC32438 DDR layout guidelines are followed.
3.
Setup times are calculated as applicable clock period - Tdo max. For example, if the DDR is running at 266MHz, it uses a 133MHz input clock. The period for a 133MHz clock is
7.5ns. If the Tdo max value is 4.5ns, the T
IS
parameter is 7.5ns minus 4.5ns = 3ns. The DDR spec for this parameter is 1ns, so there is 2ns of slack left over for board propagation.
Calculations for T
DS
are similar, but since this parameter is taken relative to the DDRDQS signals, which are referenced on both edges, the effective period with a 133MHz input
clock is only 3.75ns. So, if the max Tdo is 2.7ns, we have 3.75ns minus 2.7ns = 1.05ns for T
DS
. The DDR data sheet specs a value of 0.5ns for 266MHz, so this leaves 0.55ns slack
for board propagation delays.
Referenc
e Edge
200MHz
233MHz
266MHz
300MHz
Unit
Conditions
Timing
Diagram
Reference
Min
Max
Min
Max
Min
Max
Min
Max
Memory Bus - DDR Access
DDRDATA[31:0]
Tskew_7g
2
DDRDQSx
0.0
0.9
0.0
0.9
0.0
0.9
0.0
0.8
ns
See Figures 6
and 7.
Tdo_7k
3
1.5
3.3
1.1
2.9
0.9
2.7
0.7
2.4
ns
DDRDM[7:0]
Tdo_7l
DDRDQSx
1.5
3.3
1.1
2.9
0.9
2.7
0.7
2.4
ns
DDRDQS[3:0]
Tac
DDRCKPx
-0.75
0.75
-0.75
0.75
-0.75
0.75
-0.75
0.75
ns
DDRADDR[13:0],
DDRBA[1:0],
DDRCASN, DDRCKE,
DDRCSN[1:0],
DDROEN[3:0],
DDRRASN, DDRWEN
Tdo_7m
4
DDRCKPx
1.1
4.5
1.1
4.5
1.1
4.5
1.1
4.5
ns
Table 7 DDR SDRAM Timing Characteristics
1.
Warm reset caused by any of the conditions listed in the Warm Reset section of Chapter 3, Clocking and Initialization, in the RC32438 User Reference
Manual.
2.
The RC32438 tri-states the data bus, MDATA[15:0], and negates all memory control signals.
3.
The RC32438 negates RSTN.
4.
The RC32438 starts driving the data bus, MDATA[15:0], again, but does not sample the RSTN input.
5.
CPU begins executing by taking a MIPS soft reset exception and also starts sampling the RSTN input again.
Active
Deasserted
Active
CLK
COLDRSTN
RSTN
MDATA[15:0]
Mem Control Signals
>= 4096 CLK clock cycles
>= 4096 CLK clock cycles
to allow pull-up to drive signal high)
FFFF_FFFF
1
2
3
4
5
EXTCLK
Tdz_6d
Tzd_6d
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79RC32T335-133DHI 制造商:未知廠家 制造商全稱:未知廠家 功能描述:MICROPROCESSOR|32-BIT|QFP|208PIN|PLASTIC
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