參數(shù)資料
型號: 79RC32H435-400BCI
廠商: Integrated Device Technology, Inc.
英文描述: IDTTM InterpriseTM Integrated Communications Processor
中文描述: IDTTM InterpriseTM集成通信處理器
文件頁數(shù): 6/53頁
文件大小: 444K
代理商: 79RC32H435-400BCI
6 of 53
January 19, 2006
IDT 79RC32435
PCILOCKN
I/O
PCI Lock
. This signal is asserted by an external bus master to indicate that an
exclusive operation is occurring.
PCIPAR
I/O
PCI Parity
. Even parity of the PCIAD[31:0] bus. Driven by the bus master during
address and write Data phases. Driven by the bus target during the read data
phase.
PCIPERRN
I/O
PCI Parity Error
. If a parity error is detected, this signal is asserted by the
receiving bus agent 2 clocks after the data is received.
PCIREQN[3:0]
I/O
PCI Bus Request.
In PCI host mode with internal arbiter:
These signals are inputs whose assertion indicates to the internal RC32435
arbiter that an agent desires ownership of the PCI bus.
In PCI host mode with external arbiter:
PCIREQN[0]: asserted by the RC32435 to request ownership of the PCI bus.
PCIREQN[3:1]: unused and driven high.
In PCI satellite mode:
PCIREQN[0]: this signal is asserted by the RC32435 to request use of the PCI
bus.
PCIREQN[1]: function changes to PCIIDSEL and is used as a chip select during
configuration read and write transactions.
PCIREQN[3:2]: unused and driven high.
PCIRSTN
I/O
PCI Reset
. In host mode, this signal is asserted by the RC32435 to generate a
PCI reset. In satellite mode, assertion of this signal initiates a warmreset.
PCISERRN
I/O
PCI System Error
. This signal is driven by an agent to indicate an address par-
ity error, data parity error during a special cycle command, or any other system
error. Requires an external pull-up.
PCISTOPN
I/O
PCI Stop
. Driven by the bus target to termnate the current bus transaction. For
example, to indicate a retry.
PCITRDYN
I/O
PCI Target Ready
. Driven by the bus target to indicate that the current data can
complete.
General Purpose Input/Output
GPIO[0]
I/O
General Purpose I/O.
This pin can be configured as a general purpose I/O pin.
Alternate function pin name: U0SOUT
Alternate function: UART channel 0 serial output.
GPIO[1]
I/O
General Purpose I/O.
This pin can be configured as a general purpose I/O pin.
Alternate function pin name: U0SINP
Alternate function: UART channel 0 serial input.
GPIO[2]
I/O
General Purpose I/O.
This pin can be configured as a general purpose I/O pin.
Alternate function pin name: U0RTSN
Alternate function: UART channel 0 request to send.
GPIO[3]
I/O
General Purpose I/O.
This pin can be configured as a general purpose I/O pin.
Alternate function pin name: U0CTSN
Alternate function: UART channel 0 clear to send.
S ignal
Type
Name/Desc ription
Table 1 Pin Description (Part 3 of 6)
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