參數資料
型號: 79RC32H435-400BCI
廠商: Integrated Device Technology, Inc.
英文描述: IDTTM InterpriseTM Integrated Communications Processor
中文描述: IDTTM InterpriseTM集成通信處理器
文件頁數: 2/53頁
文件大?。?/td> 444K
代理商: 79RC32H435-400BCI
2 of 53
January 19, 2006
IDT 79RC32435
N
Non-Volatile RAM
Provides 512-bits of non-volatile storage
Elimnates need for external boot configuration vector
Stores initial PCI configuration register values when PCI
configured to operate in satellite mode with suspended CPU
execution
Authorization unit ensures only authorized software will
operate on the system
N
Memory and Peripheral Device Controller
Provides “glueless” interface to standard SRAM Flash, ROM
dual-port memory, and peripheral devices
Demultiplexed address and data buses: 8-bit data bus, 26-bit
address bus, 4 chip selects, control for external data bus
buffers
Automatic byte gathering and scattering
Flexible protocol configuration parameters: programmable
number of wait states (0 to 63), programmable postread/post-
write delay (0 to 31), supports external wait state generation,
supports Intel and Motorola style peripherals
Write protect capability per chip select
Programmable bus transaction timer generates warmreset
when counter expires
Supports up to 64 MB of memory per chip select
N
DMA Controller
6 DMA channels: two channels for PCI (PCI to Memory and
Memory to PCI), two channels for the Ethernet interface, and
two channels for memory to memory DMA operations
Provides flexible descriptor based operation
Supports unaligned transfers (i.e., source or destination
address may be on any byte boundary) with arbitrary byte
length
N
Universal Asynchronous Receiver Transmitter (UART)
Compatible with the 16550 and 16450 UARTs
16-byte transmt and receive buffers
Programmable baud rate generator derived fromthe system
clock
Fully programmable serial characteristics:
5, 6, 7, or 8 bit characters
Even, odd or no parity bit generation and detection
1, 1-1/2 or 2 stop bit generation
Line break generation and detection
False start bit detection
Internal loopback mode
N
I
2
C-Bus
Supports standard 100 Kbps mode as well as 400 Kbps fast
mode
Supports 7-bit and 10-bit addressing
Supports four modes: master transmtter master receiver
slave transmtter slave receiver
N
Additional General Purpose Peripherals
Interrupt controller
Systemintegrity functions
General purpose I/O controller
Serial peripheral interface (SPI)
N
Counter/Timers
Three general purpose 32-bit counter timers
Timers may be cascaded
Selectable counter/timer clock source
N
JTAG Interface
Compatible with IEEE Std. 1149.1 - 1990
C PU Execution Core
The 32-bit CPU core is 100% compatible with the MIPS32 instruction
set architecture (ISA). Specifically, this device features the 4Kc CPU
core developed by MIPS Technologies Inc. (wwwmps.com. This core
issues a single instruction per cycle, includes a five stage pipeline and is
optimzed for applications that require integer arithmetic.
The CPU core includes 8 KB instruction and 8 KB data caches. Both
caches are 4-way set associative and can be locked on a per line basis,
which allows the programmer control over this precious on-chip memory
resource. The core also features a memory management unit (MMU).
The CPU core also incorporates an enhanced joint test access group
(EJTAG) interface that is used to interface to in-circuit emulator tools,
providing access to internal registers and enabling the part to be
controlled externally, simplifying the systemdebug process.
The use of this core allows IDT's customers to leverage the broad
range of software and development tools available for the MIPS archi-
tecture, including operating systems, compilers, and in-circuit emula-
tors.
PCI Interface
The PCI interface on the RC32435 is compatible with version 2.2 of
the PCI specification. An on-chip arbiter supports up to six external bus
masters, supporting both fixed priority and rotating priority arbitration
schemes. The part can support both satellite and host PCI configura-
tions, enabling the RC32435 to act as a slave controller for a PCI add-in
card application or as the primary PCI controller in the system The PCI
interface can be operated synchronously or asynchronously to the other
I/O interfaces on the RC32435 device.
Ethernet Interfac e
The RC32435 has one Ethernet Channel supporting 10Mbps and
100Mbps speeds to provide a standard media independent interface
(MII or RMII), allowing a wide range of external devices to be connected
efficiently.
Double Data Rate Memory Controller
The RC32435 incorporates a high performance double data rate
(DDR) memory controller which supports x16 memory configurations up
to 256MB. This module provides all of the signals required to interface
to discrete memory devices, including a chip select, differential clocking
outputs and data strobes.
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