參數(shù)資料
型號(hào): 79RC32435
廠商: Integrated Device Technology, Inc.
英文描述: IDTTM InterpriseTM Integrated Communications Processor
中文描述: IDTTM InterpriseTM集成通信處理器
文件頁(yè)數(shù): 27/53頁(yè)
文件大小: 444K
代理商: 79RC32435
27 of 53
January 19, 2006
IDT 79RC32435
S ignal
S ymbol
Referenc e
Edge
266MHz
300MHz
350MHz
400MHz
Unit
Condi-
tions
T iming
Diagram
Referenc e
Mn
Max
Min
Max
Mn
Max
Mn
Max
PCI
1
1.
This PCI interface conforms to the PCI Local Bus Specification, Rev 2.2.
2.
PCICLK must be equal to or less than two times ICLK (PCICLK <= 2(ICLK)) with a maximumPCICLK of 66 MHz.
3.
The values for this symbol were determned by calculation, not by testing.
4.
PCIRSTN is an output in host mode and an input in satellite mode.
5.
To meet the PCI delay specification fromreset asserted to outputs floating, the PCI reset should be logically combined with the COLDRSTN input, instead of input on PCIRSTN.
6.
PCISERRN and PCIMUINTN use open collector I/O types.
PCICLK
2
Tper_10a
none
15.0
30.0
15.0
30.0
15.0
30.0
15.0
30.0
ns
66 MHz
PCI
See Figure 11.
Thigh_10a,
Tlow_10a
6.0
6.0
6.0
6.0
ns
Tslew_10a
1.5
4.0
1.5
4.0
1.5
4.0
1.5
4.0
V/ns
PCIAD[31:0],
PCIBEN[3:0],
PCIDEVSELN,
PCIFRA-
MEN,PCIIR-
DYN,
PCILOCKN,
PCIPAR, PCI-
PERRN, PCIS-
TOPN,
PCITRDY
Tsu_10b
PCICLK rising
3.0
3.0
3.0
3.0
ns
Thld_10b
0
0
0
0
ns
Tdo_10b
2.0
6.0
2.0
6.0
2.0
6.0
2.0
6.0
ns
Tdz_10b
3
14.0
14.0
14.0
14.0
ns
Tzd_10b
3
2.0
2.0
2.0
2.0
ns
PCIGNTN[3:0],
PCIREQN[3:0]
Tsu_10c
PCICLK rising
5.0
5.0
5.0
5.0
ns
Thld_10c
0
0
0
0
ns
Tdo_10c
2.0
6.0
2.0
6.0
2.0
6.0
2.0
6.0
ns
PCIRSTN (out-
put)
4
Tpw_10d
3
None
4000
(CLK)
4000
(CLK)
4000
(CLK)
4000
(CLK)
ns
See Figures 15
and 16
PCIRSTN
(input)
4,5
Tpw_10e
3
None
2(CLK)
2(CLK)
2(CLK)
2(CLK)
ns
Tdz_10e
3
PCIRSTN
falling
6(CLK)
6(CLK)
6(CLK)
6(CLK)
ns
PCISERRN
6
Tsu_10f
PCICLK rising
3.0
3.0
3.0
3.0
ns
See Figure 11
Thld_10f
0
0
0
0
ns
Tdo_10f
2.0
6.0
2.0
6.0
2.0
6.0
2.0
6.0
ns
PCIMUINTN
6
Tdo_10g
PCICLK rising
4.7
11.1
4.7
11.1
4.7
11.1
4.7
11.1
ns
Table 10 PCI AC Timing Characteristics
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