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參數(shù)資料
| 型號： | 79RC32435 |
| 廠商： | Integrated Device Technology, Inc. |
| 英文描述： | IDTTM InterpriseTM Integrated Communications Processor |
| 中文描述： | IDTTM InterpriseTM集成通信處理器 |
| 文件頁數(shù)： | 12/53頁 |
| 文件大?。?/td> | 444K |
| 代理商： | 79RC32435 |
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January 19, 2006
IDT 79RC32435
Boot Configuration Vec tor
The encoding of the boot configuration vector is described in Table 3, and the vector input is illustrated in Figure 4. The value of the boot configura-
tion vector read in by the RC32435 during a cold reset may be determned by reading the Boot Configuration Vector (BCV) Register.
S ignal
Name/Desc ription
MADDR[3:0]
CPU Pipeline Clock Multiplier
. This field specifies the value by which the PLL multi-
plies the master clock input (CLK) to obtain the processor clock frequency (PCLK). For
master clock input frequency constraints, refer to Table 3.2
in the RC32435 User Man-
ual.
0x0 - PLL Bypass
0x1 - Multiply by 3
0x2 - Multiply by 4
0x3 - Multiply by 5 - Reserved
0x4 - Multiply by 5
0x5 - Multiply by 6 - Reserved
0x6 - Multiply by 6
0x7 - Multiply by 8
0x8 - Multiply by 10
0x9 through 0xF - Reserved
MADDR[5:4]
External Clock Divider
. This field specifies the value by which the IPBus clock
(ICLK), which is always 1/2 PCLK, is divided in order to generate the external clock
output on the EXTCLK pin.
0x0 - Divide by 1
0x1 - Divide by 2
0x2 - Divide by 4
0x3 - reserved
MADDR[6]
Endian.
This bit specifies the endianness.
0x0 - little endian
0x1 - big endian
MADDR[7]
Reset Mode
. This bit specifies the length of time the RSTN signal is driven.
0x0 - Normal reset: RSTN driven for mnimumof 4000 clock cycles. If the internal boot
configuration vector is selected, the expiration of an 18-bit counter operating at the
master clock input (CLK) frequency is used as the PLL stabilization delay.
0x1 - Reserved
MADDR[10:8]
PCI Mode
. This bit controls the operating mode of the PCI bus interface. The initial
value of the EN bit in the PCIC register is determned by the PCI mode.
0x0 - Disabled (EN initial value is zero)
0x1 - PCI satellite mode with PCI target not ready (EN initial value is one)
0x2 - PCI satellite mode with suspended CPU execution (EN initial value is one)
0x3 - PCI host mode with external arbiter (EN initial value is zero)
0x4 - PCI host mode with internal arbiter using fixed priority arbitration algorithm
(EN initial value is zero)
0x5 - PCI host mode with internal arbiter using round robin arbitration algorithm
(EN initial value is zero)
0x6 -
reserved
0x7 -
reserved
Table 3 Boot Configuration Encoding (Part 1 of 2)
相關PDF資料 |
PDF描述 |
|---|---|
| 79RC32H435-266BC | IDTTM InterpriseTM Integrated Communications Processor |
| 79RC32H435-266BCI | IDTTM InterpriseTM Integrated Communications Processor |
| 79RC32H435-300BC | IDTTM InterpriseTM Integrated Communications Processor |
| 79RC32H435-300BCI | IDTTM InterpriseTM Integrated Communications Processor |
| 79RC32H435-350BC | IDTTM InterpriseTM Integrated Communications Processor |
相關代理商/技術參數(shù) |
參數(shù)描述 |
|---|---|
| 79RC32438 | 制造商:IDT 制造商全稱:Integrated Device Technology 功能描述:IDTTM InterpriseTM Integrated Communications Processor |
| 79RC32438-200BB | 制造商:未知廠家 制造商全稱:未知廠家 功能描述:Microprocessor |
| 79RC32438-200BBI | 制造商:未知廠家 制造商全稱:未知廠家 功能描述:Microprocessor |
| 79RC32438-233BB | 制造商:未知廠家 制造商全稱:未知廠家 功能描述:Microprocessor |
| 79RC32438-233BBI | 制造商:未知廠家 制造商全稱:未知廠家 功能描述:Microprocessor |
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