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參數(shù)資料
| 型號(hào)： | 79RC32355 |
| 廠商： | Integrated Device Technology, Inc. |
| 英文描述： | Communications Processor |
| 中文描述： | 通信處理器 |
| 文件頁(yè)數(shù)： | 17/47頁(yè) |
| 文件大?。?/td> | 987K |
| 代理商： | 79RC32355 |
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17 of 47
May 25, 2004
IDT 79RC32355
AC Timing Characteristics
(Ta = 0
°
C to +70
°
C Commercial, Ta = -40
°
C to +85
°
C Industrial, Vcc I/O = +3.3V
±
5%,V
cc
Core = +2.5V
±
5%, V
cc
P = +2.5V
±
5%)
Signal
Symbol
Reference
Edge
133MHz
150MHz
180MHz
Unit
Conditions
Timing
Diagram
Reference
Min
Max
Min
Max
Min
Max
Reset and System
COLDRSTN
Tpw1
none
110
110
—
110
—
ms
Figure 6
Figure 7
Trise1
none
—
5.0
—
5.0
—
5.0
ns
RSTN
1
Tdo2
CLKP rising
4.0
10.7
4.0
10.7
4.0
10.7
ns
MDATA[15:0]
Boot Configuration
Vector
Thld3
COLDRSTN
rising
3
—
3
—
3
—
ns
INSTP
Tdo
CLKP rising
5.0
8.0
5.0
8.0
5.0
8.0
ns
CPUP
Tdo
CLKP rising
3.5
7.0
3.5
7.0
3.5
7.0
ns
DMAP
Tdo
CLKP rising
3.5
6.6
3.5
6.6
3.5
6.6
ns
DMAREQN
2
Tpw
none
(CLKP+7)
—
(CLKP+7)
—
(CLKP+7)
—
ns
DMADONEN
2
Tpw
none
(CLKP+7)
—
(CLKP+7)
—
(CLKP+7)
—
ns
DMAFIN
Tdo
CLKP rising
3.5
5.9
3.5
5.9
3.5
5.9
ns
BRN
Tsu
CLKP rising
1.6
—
1.6
—
1.6
—
ns
Thld
0
—
0
—
0
—
ns
BGN
Tdo
CLKP rising
3.3
5.8
3.3
5.8
3.3
5.8
ns
1
RSTN is a bidirectional signal. It is treated as an asynchronous input.
2
DMAREQN and DMADONEN minimum pulse width equals the CLKP period plus 7ns.
Table 5 Reset and System AC Timing Characteristics
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相關(guān)代理商/技術(shù)參數(shù) |
參數(shù)描述 |
|---|---|
| 79RC32355133DH | 制造商:IDT 制造商全稱:Integrated Device Technology 功能描述:Communications Processor |
| 79RC32355-133DH | 制造商:IDT 制造商全稱:Integrated Device Technology 功能描述:Communications Processor |
| 79RC32355133DHI | 制造商:IDT 制造商全稱:Integrated Device Technology 功能描述:Communications Processor |
| 79RC32355-133DHI | 制造商:IDT 制造商全稱:Integrated Device Technology 功能描述:IDT Interprise Integrated Communications Processor |
| 79RC32355150DH | 制造商:IDT 制造商全稱:Integrated Device Technology 功能描述:Communications Processor |
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