參數(shù)資料
型號(hào): 79RC32355180DH
廠商: Integrated Device Technology, Inc.
英文描述: Communications Processor
中文描述: 通信處理器
文件頁(yè)數(shù): 20/47頁(yè)
文件大小: 987K
代理商: 79RC32355180DH
20 of 47
May 25, 2004
IDT 79RC32355
Note:
The RC32355 provides bus turnaround cycles to prevent bus contention when going from a read to write, write to read, and during
external bus ownership. For example, there are no cycles where an external device and the RC32355 are both driving. See the chapters
“Device Controller,” “Synchronous DRAM Controller,” and “Bus Arbitration” in the RC32355 User Reference Manual.
Memory and Peripheral Bus - Device Access
MDATA[31:0]
Tsu1
CLKP rising
2.5
2.5
2.5
ns
Figure 11
Figure 12
Thld1
1.5
1.5
1.5
ns
Tdo1
2.0
6.5
2.0
6.5
2.0
6.5
ns
Tdz1
9.0
9.0
9.0
ns
Tzd1
2.0
2.0
2.0
ns
WAITACKN, BRN
Tsu
CLKP rising
2.5
2.5
2.5
ns
Thld
1.5
1.5
1.5
ns
MADDR[21:0]
Tdo2
CLKP rising
2.0
6.0
2.0
6.0
2.0
6.0
ns
Tdz2
9.0
9.0
9.0
ns
Tzd2
2.0
2.0
2.0
ns
MADDR[25:22]
Tdo3
CLKP rising
2.5
6.5
2.5
6.5
2.5
6.5
ns
Tdz3
9.0
9.0
9.0
ns
Tzd3
2.0
2.0
2.0
ns
BDIRN, BOEN[0]
Tdo4
CLKP rising
2.0
6.0
2.0
6.0
2.0
6.0
ns
Tdz4
9.0
9.0
9.0
ns
Tzd4
2.0
2.0
2.0
ns
BGN, BWEN[3:0], OEN,
RWN
Tdo5
CLKP rising
2.0
6.0
2.0
6.0
2.0
6.0
ns
Tdz5
9.0
9.0
9.0
ns
Tzd5
2.0
2.0
2.0
ns
CSN[3:0]
Tdo6
CLKP rising
1.7
5.0
1.7
5.0
1.7
5.0
ns
Tdz6
9.0
9.0
9.0
ns
Tzd6
2.0
2.0
2.0
ns
CSN[5:4]
Tdo7
CLKP rising
2.5
6.0
2.5
6.0
2.5
6.0
ns
Tdz7
9.0
9.0
9.0
ns
Tzd7
2.0
2.0
2.0
ns
Signal
Symbol
Reference
Edge
133MHz
150MHz
180MHz
Unit
Conditions
Timing
Diagram
Reference
Min
Max
Min
Max
Min
Max
Table 6 Memory and Peripheral Bus AC Timing Characteristics (Part 2 of 2)
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