參數(shù)資料
型號(hào)： 79RC32355150DH
廠商： Integrated Device Technology, Inc.
英文描述： Communications Processor
中文描述： 通信處理器
文件頁(yè)數(shù)： 38/47頁(yè)
文件大?。?/td> 987K
代理商： 79RC32355150DH
38 of 47
May 25, 2004
IDT 79RC32355
Phase-Locked Loop (PLL)
The processor aligns the pipeline clock, PClock, to the master input clock (CLKP) by using an internal phase-locked loop (PLL) circuit that gener-
ates aligned clocks. Inherently, PLL circuits are only capable of generating aligned clocks for master input clock (CLKP) frequencies within a limited
range.
PLL Analog Filter
The storage capacitor required for the Phase-Locked Loop circuit is contained in the RC32355. However, it is recommended that the system
designer provide a filter network of passive components for the PLL power supply.
V
CC
P (PLL circuit power) and V
SS
P (PLL circuit ground) should be isolated from V
CC
Core (core power) and V
SS
(common ground) with a filter
circuit such as the one shown in Figure 22.
Because the optimum values for the filter components depend upon the application and the system noise environment, these values should be
considered as starting points for further experimentation within your specific application.
Figure 22 PLL Filter Circuit for Noisy Environments
Recommended Operating Temperature and Supply Voltage
Capacitive Load Deration
RC32355 IBIS Model
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