參數(shù)資料
型號: 79RC32351
廠商: Integrated Device Technology, Inc.
英文描述: IDT Interprise Integrated Communications Processor
中文描述: IDT的洽談會集成通信處理器
文件頁數(shù): 18/42頁
文件大?。?/td> 560K
代理商: 79RC32351
18 of 42
May 25, 2004
IDT 79RC32351
Figure 7 Warm Reset AC Timing Waveform
Active
Deasserted
Active
CLKP
COLDRSTN
RSTN
MDATA[31:0]
Mem Control Signals
>= 4096 CLKP clock cycles
OR
>= 64 CLKP clock cycles
*
>= 4096 CLKP clock cycles
OR
>= 64 CLKP clock cycles
(RSTN ignored during this period
to allow pull-up to drive signal high)
*
Selection of 4096 or 64 cycles is selected by the boot configuration vector (fast reset).
1.
Warm reset condition caused by either RSTN asserted, write to reset register, or bus transaction timer time-out. The RC32351 asserts RSTN out-
put low in response.
2.
The RC32351 tri-states the data bus, MDATA[31:0], and deasserts all memory control signals, such as RASN, CASN, RWN, OEN, etc.
3.
The RC32351 deasserts RSTN.
4.
The RC32351 starts driving the data bus, MDATA[31:0], again, but does not sample the RSTN input.
5.
CPU begins executing by taking a MIPS soft reset exception and also starts sampling the RSTN input again.
FFFF_FFFF
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79RC32351-100DH IDT Interprise Integrated Communications Processor
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79RC32351-100DH 制造商:IDT 制造商全稱:Integrated Device Technology 功能描述:IDT Interprise Integrated Communications Processor
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