參數(shù)資料
型號： 79RC32351
廠商： Integrated Device Technology, Inc.
英文描述： IDT Interprise Integrated Communications Processor
中文描述： IDT的洽談會集成通信處理器
文件頁數(shù)： 12/42頁
文件大?。?/td> 560K
代理商： 79RC32351
12 of 42
May 25, 2004
IDT 79RC32351
Signal
Name/Description
MDATA[2:0]
Clock Multiplier
. This field specifies the value by which the system clock (CLKP) is multiplied internally to generate the CPU pipeline clock.
0x0 - multiply by 2
0x1 - multiply by 3
0x2 - multiply by 4
0x3 - reserved
0x4 - reserved
0x5 - reserved
0x6 - reserved
0x7 - reserved
MDATA[3]
Endian.
This bit specifies the endianness of RC32351.
0x0 - little endian
0x1 - big endian
MDATA[4]
Reserved.
Must be set to 0.
MDATA[5]
Debug Boot Mode
. When this bit is set, the RC32351 begins executing from address 0xFF20_0200 rather than 0xBFC0_0000 following a reset.
0x0 - regular mode (processor begins executing at 0xBFC0_0000)
0x1 - debug boot mode (processor begins executing at 0xFF20_0200)
MDATA[7:6]
Boot Device Width
. This field specifies the width of the boot device.
0x0 - 8-bit boot device width
0x1 - 16-bit boot device width
0x2 - 32-bit boot device width
0x3 - reserved
MDATA[8]
EJTAG/ICE Interface Enable
. When this bit is set, Alternate 2 pin functions EJTAG_PCST[2:0], EJTAG_DCLK, and EJTAG_TRST_N are
selected.
0x0 - GPIOP[31, 13:10] pins behaves as GPIOP
0x1 - GPIOP[31] pin behaves as EJTAG_TRST_N,
GPIOP[12:10] pins behave as EJTAG_PCST[2:0], and
GPIOP[13] pin behaves as EJTAG_DCLK
MDATA[9]
Fast Reset
. When this bit is set, RC32351 drives RSTN for 64 clock cycles, used during test only. Clear this bit for normal operation.
0x0 - Normal reset: RC32351 drives RSTN for minimum of 4096 clock cycles
0x1 - Fast Reset: RC32351 drives RSTN for 64 clock cycles (test only)
MDATA[10]
DMA Debug Enable
. When this bit is set, Alternate 2 pin function, DMAP is selected. DMAP provides the DMA channel number during memory
and peripheral bus DMA transactions.
0x0 - GPIOP[8, 9, 25, 23] pins behave as GPIOP
0x1 - GPIOP[8, 9, 25, 23] pins behave as DMAP[3:0]
MDATA[11]
Hold SYSCLKP Constant
. For systems that do not require a SYSCLKP output and can instead use CLKP, setting this bit to a one causes the
SYSCLKP output to be held at a constant level. This may be used to reduce EMI.
0x0 - Allow SYSCLKP to toggle
0x1 - Hold SYSCLKP constant
MDATA[12]
JTAG Boundary Scan Reset Enable
. When this bit is set, Alternate 2 pin function, JTAG_TRST_N is selected.
0x0 - GPIOP[2] pin behaves as GPIOP
0x1 - GPIOP[2] pin behaves as JTAG_TRST_N
MDATA[13]
CPU / DMA Transaction Indicator Enable
. When this bit is set, Alternate 2 pin function, CPUP is selected.
0x0 - GPIOP[4] pin behaves as GPIOP
0x1 - GPIOP[4] pin behaves as CPUP
MDATA[15:14]
Reserved
. These pins must be driven low during boot configuration.
Table 2 Boot Configuration Vector Encoding
相關(guān)PDF資料
PDF描述
79RC32351-100DH IDT Interprise Integrated Communications Processor
79RC32351-133DH IDT Interprise Integrated Communications Processor
79RC32355-133DH Communications Processor
79RC32355-133DHI Communications Processor
79RC32T355-133DH IDT Interprise Integrated Communications Processor
相關(guān)代理商/技術(shù)參數(shù)
參數(shù)描述
79RC32351-100DH 制造商:IDT 制造商全稱:Integrated Device Technology 功能描述:IDT Interprise Integrated Communications Processor
79RC32351-133DH 制造商:IDT 制造商全稱:Integrated Device Technology 功能描述:IDT Interprise Integrated Communications Processor
79RC32355 制造商:IDT 制造商全稱:Integrated Device Technology 功能描述:Communications Processor
79RC32355133DH 制造商:IDT 制造商全稱:Integrated Device Technology 功能描述:Communications Processor
79RC32355-133DH 制造商:IDT 制造商全稱:Integrated Device Technology 功能描述:Communications Processor
發(fā)布緊急采購，3分鐘左右您將得到回復(fù)。

采購需求

(若只采購一條型號，填寫一行即可)

發(fā)布成功！您可以繼續(xù)發(fā)布采購。也可以進(jìn)入我的后臺，查看報價

發(fā)布成功！您可以繼續(xù)發(fā)布采購。也可以進(jìn)入我的后臺，查看報價

*型號 *數(shù)量 廠商 批號 封裝
添加更多采購

我的聯(lián)系方式

*
*
*