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參數(shù)資料
| 型號： | 795T |
| 廠商： | 意法半導(dǎo)體 |
| 英文描述： | 3V Supervisor with Battery Switchover |
| 中文描述： | 3V的監(jiān)控與電池切換 |
| 文件頁數(shù)： | 9/32頁 |
| 文件大?。?/td> | 304K |
| 代理商： | 795T |
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STM690/704/795/802/804/805/806
OPERATION
Reset Output
The STM690/704/795/802/804/805/806 Supervi-
sor asserts a reset signal to the MCU whenever
V
CC
goes below the reset threshold (V
RST
), a
watchdog time-out occurs, or when the Push-but-
ton Reset Input (MR) is taken low. RST is guaran-
teed to be a logic low (logic high for STM804/805)
for 0V < V
CC
< V
RST
if V
BAT
is greater than 1V.
Without a back-up battery, RST is guaranteed val-
id down to V
CC
=1V.
During power-up, once V
CC
exceeds the reset
threshold an internal timer keeps RST low for the
reset time-out period, t
rec
. After this interval RST
returns high.
If V
CC
drops below the reset threshold, RST goes
low. Each time RST is asserted, it stays low for at
least the reset time-out period (t
rec
). Any time V
CC
goes below the reset threshold the internal timer
clears. The reset timer starts when V
CC
returns
above the reset threshold.
Push-button Reset Input (STM704/806)
A logic low on MR asserts reset. Reset remains
asserted while MR is low, and for t
rec
(see
Figure
37., page 24
) after it returns high. The MR input
has an internal 40k
pull-up resistor, allowing it to
be left open if not used. This input can be driven
with TTL/CMOS-logic levels or with open-drain/
collector outputs. Connect a normally open mo-
mentary switch from MR to GND to create a man-
ual reset function; external debounce circuitry is
not required. If MR is driven from long cables or
the device is used in a noisy environment, connect
a 0.1μF capacitor from MR to GND to provide ad-
ditional noise immunity. MR may float, or be tied to
V
CC
when not used.
Watchdog Input (NOT available on STM704/
795/806)
The watchdog timer can be used to detect an out-
of-control MCU. If the MCU does not toggle the
Watchdog Input (WDI) within t
WD
(1.6sec typ), the
reset is asserted. The internal watchdog timer is
cleared by either:
1.
a reset pulse, or
2.
by toggling WDI (high-to-low or low-to-high),
which can detect pulses as short as 50ns. If
WDI is tied high or low, a reset pulse is
triggered every 1.8sec (t
WD
+ t
rec
).
The timer remains cleared and does not count for
as long as reset is asserted. As soon as reset is re-
leased, the timer starts counting (see
Figure
38., page 24
).
Note:
Input frequency greater than 20ns (50MHz)
will be filtered.
Back-up Battery Switchover
In the event of a power failure, it may be necessary
to preserve the contents of external SRAM
through V
OUT
. With a backup battery installed with
voltage V
BAT
, the devices automatically switch the
SRAM to the back-up supply when V
CC
falls.
Note:
If back-up battery is not used, connect both
V
BAT
and V
OUT
to V
CC
.
This family of Supervisors does not always con-
nect V
BAT
to V
OUT
when V
BAT
is greater than V
CC
.
V
BAT
connects to V
OUT
(through a 100
switch)
when V
CC
is below V
SW
(2.4V) or V
BAT
(whichever
is lower). This is done to allow the back-up battery
(e.g., a 3.6V lithium cell) to have a higher voltage
than V
CC
.
Assuming that V
BAT
> 2.0V, switchover at V
SO
en-
sures that battery back-up mode is entered before
V
OUT
gets too close to the 2.0V minimum required
to reliably retain data in most external SRAMs.
When V
CC
recovers, hysteresis is used to avoid
oscillation around the V
SO
point. V
OUT
is connect-
ed to V
CC
through a 3
PMOS power switch.
Note:
The back-up battery may be removed while
V
CC
is valid, assuming V
BAT
is adequately decou-
pled (0.1μF typ), without danger of triggering a re-
set.
Table 4. I/O Status in Battery Back-up
Pin
Status
V
OUT
Connected to V
BAT
through internal switch
V
CC
Disconnected from V
OUT
PFI
Disabled
PFO
Logic Low
E
High impedance
E
CON
Logic High
WDI
Watchdog timer is disabled
MR
Disabled
RST
Logic Low
RST
Logic High
V
BAT
Connected to V
OUT
Vccsw
Logic High (STM795)
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