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參數(shù)資料
| 型號(hào)： | 78Q2120-64CG |
| 廠商： | Electronic Theatre Controls, Inc. |
| 英文描述： | 10/100BASE-TX Ethernet Transceiver |
| 中文描述： | 10/100BASE-TX以太網(wǎng)收發(fā)器 |
| 文件頁數(shù)： | 3/33頁 |
| 文件大?。?/td> | 200K |
| 代理商： | 78Q2120-64CG |
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78Q2120
10/100BASE-TX
Ethernet Transceiver
100BASE-TX OPERATION
3
100BASE-TX Transmit
The 78Q2120 contains all of the necessary circuitry
to convert the transmit MII signaling from a MAC to
an IEEE-802.3 compliant data-stream driving Cat-5
UTP cabling. The internal PCS interface maps 4 bit
nibbles from the MII to 5 bit code groups as defined
in table 24-1 of IEEE-802.3. These 5 bit code groups
are then scrambled and converted to a serial stream
before being sent to the MLT-3 pulse shaping
circuitry and line driver. The pulse-shaper uses
current modulation to produce the desired output
waveform. Controlled rise/fall time in MLT-3 signal
is achieved using an accurately controlled C/I filter.
The line driver requires an external 1:1 isolation
transformer to interface with the line media. The
center-tap of the primary side of the transformer
should be connected to Vcc.
100BASE-TX RECEIVE
The 78Q2120 receives a 125MBaud MLT-3 signal
through a 1:1 transformer. The signal then goes through
a combination of adaptive offset adjustment (baseline
wander correction) and adaptive equalization. The
effect of these circuits is to sense the amount of
dispersion and attenuation caused by the cable and
transformer, and restore the received pulses to logic
levels. The amount of gain and equalization applied to
the pulses varies with the detected attenuation and
dispersion and, therefore, with the length of the cable.
The 78Q2120 can recover up to a 10dB of loss in signal
amplitude at 16 MHz. This loss is represented as test-
chan 5 in AnnexA of the ANSI X3.263:199X
specification and corresponds to approximately 140m of
Cat5 UTP cabling. The equalized MLT-3 data signal is
sliced and the resulting bit-stream is presented to the
clock recovery PLL and to a serial to parallel converter.
The parallel data from the converter is then descrambled
and aligned into 5 bit code groups. The receive PCS
interface maps these code groups to 4 bit data for the
MII as outlined in table 24-1 in Clause 24 of IEEE-802.3
PCS BYPASS MODE
The PCS Bypass mode is entered by pulling PCSBP
high or by setting register bit MR 16.1. In this mode
the 78Q2120 accepts scrambled 5 bit code into the
pins TX_ER and TXD[3:0]. TX_ER is the MSB data
input. The 5 bit code groups are converted to an
MLT-3 signal. The received MLT-3 signal is
converted to 5 bit NRZ code groups and output from
the RX_ER and RXD[3:0] pins. The RX_ER pin is
the MSB data output. The RX_DV and TX_EN pins
are unused in pcs bypass mode.
10BASE-T OPERATION
10BASE-T TRANSMIT
The 78Q2120 takes 4 bit parallel NRZ data via the
MII interface and passes it through a parallel to
serial converter. The data is then passed through a
Manchester encoder and then on to the twisted pair
pulse shaping circuitry and the twisted pair drive
circuitry. An advanced pulse shaper employs a Gm-
C filter to pre-distort the output waveform to meet the
output voltage template and spectral content
requirements detailed in Clause 14 of IEEE-802.3.
Interface to the twisted pair media is through two
external 50 ohm resistors and a center-tapped 1:1
transformer; no external filtering is required. During
auto-negotiation and during 10BASE-T idle periods,
link pulses are transmitted.
The 78Q2120 employs an onboard timer to prevent
the
MAC
from
capturing
excessively long transmissions. When this timer is
exceeded the chip enters the jabber state, and
transmission is disabled. The jabber state is exited
after the MII goes idle for 500ms
±
250ms.
a
network
through
10BASE-T RECEIVE
The
78Q2120
10BASE-T data through the twisted pair inputs and
re-establishes logic levels through a slicer with a
smart squelch function. The slicer automatically
adjusts its level after valid data with the appropriate
levels are detected. Data is passed on to the
10BASE-T PLL where the clock is recovered, data is
re-timed and passed through a Manchester decoder.
From here data enters the serial to parallel converter
for transmission to the MAC via the media
independent interface. Interface to the twisted pair
media is through an external 100 ohm resistor and a
1:1 center-tapped transformer; no external filtering is
required. Polarity information is detected and
corrected in the internal circuitry.
receives
Manchester
encoded
POLARITY CORRECTION
The 78Q2120 is capable of either automatic or
manual polarity reversal for 10BASE-T and auto-
negotiation. These features are controlled by
register bits MR16.5 and MR16.4. The default is
automatic mode where MR16.5 is low and MR16.4
indicates if the detection circuitry has inverted the
input signal. To enter manual mode, MR16.5 is set
high and MR16.4 will then control the signal polarity.
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PDF描述 |
|---|---|
| 78Q2120-64CGT | 10/100BASE-TX Ethernet Transceiver |
| 78Q2120-64T | 10/100BASE-TX Ethernet Transceiver |
| 78Q2120-CGT | 10/100BASE-TX Ethernet Transceiver |
| 78Q8392L | Low Power Ethernet Coaxial Transceiver |
| 78Q8392L-28CH | Low Power Ethernet Coaxial Transceiver |
相關(guān)代理商/技術(shù)參數(shù) |
參數(shù)描述 |
|---|---|
| 78Q2120-64CGT | 制造商:未知廠家 制造商全稱:未知廠家 功能描述:10/100BASE-TX Ethernet Transceiver |
| 78Q2120-64T | 制造商:未知廠家 制造商全稱:未知廠家 功能描述:10/100BASE-TX Ethernet Transceiver |
| 78Q2120C | 制造商:TDK 制造商全稱:TDK Electronics 功能描述:10/100BASE - TX Transceiver |
| 78Q2120C09-64CGT | 制造商:TERIDIAN 制造商全稱:TERIDIAN 功能描述:10/100BASE-TX Transceiver |
| 78Q2120C09-64CGT/F | 功能描述:以太網(wǎng) IC 10-100 Fast Ethernet Transceiver RoHS:否 制造商:Micrel 產(chǎn)品:Ethernet Switches 收發(fā)器數(shù)量:2 數(shù)據(jù)速率:10 Mb/s, 100 Mb/s 電源電壓-最大:1.25 V, 3.45 V 電源電壓-最小:1.15 V, 3.15 V 最大工作溫度:+ 85 C 封裝 / 箱體:QFN-64 封裝:Tray |
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