參數(shù)資料
型號： 78Q2120-64CG
廠商： Electronic Theatre Controls, Inc.
英文描述： 10/100BASE-TX Ethernet Transceiver
中文描述： 10/100BASE-TX以太網(wǎng)收發(fā)器
文件頁數(shù)： 15/33頁
文件大?。?/td> 200K
代理商： 78Q2120-64CG
78Q2120
10/100BASE-TX
Ethernet Transceiver
MR16 - VENDOR SPECIFIC REGISTER
15
BIT
SYMBOL
TYPE
DESCRIPTION
16.15
RPTR
R, W, (0)
REPEATER MODE: When set, this bit puts the chip into repeater
mode. In this mode, full duplex is prohibited, CRS responds to
receive activity only and, in 10BASE-T mode, the SQE test function
is disabled.
16.14
INT LEVEL
R, W, 0
When this bit is a zero, the INTR pin is forced low to signal an
interrupt. Setting this bit causes the INTR pin to be forced high to
signal an interrupt.
16.13
RSVD
R, 0
RESERVED
16.12
TXHIM
R, W, 0
TRANSMIT HIGH IMPEDANCE: When this bit is set, the transmitter
UTP drivers are in a high impedance state and TXCLK is tri-stated.
The receive circuitry remains fully functional. Only a reset condition
will automatically clear this bit.
16.11
SQE TEST
INHIBIT
R, W, 0
Setting this bit disables 10BASE-T SQE testing. By default, when
this bit is a zero, the SQE test is performed by generating a COL
pulse following the completion of a packet transmission.
16.10
10BT
NATURAL
LOOPBACK
R, W, 0
Setting this bit causes transmitted data on TXD to be automatically
looped back to the RXD receive signals when 10BASE-T mode is
enabled.
16.9
GPIO1_DAT
R, W, 0
GENERAL PURPOSE I/O 1 DATA BIT: When the GPIO_DIR is set,
this bit reflects the value of the GPIO1 pin. When the GPIO1_DIR is
reset, the value of this bit is driven onto the GPIO1 pin. (80-pin
TQFP only)
16.8
GPIO1_DIR
R, W, 1
GENERAL PURPOSE I/O 1 DIRECTION BIT: Setting this bit
configures the GPIO1 pin as an input. Resetting configures GPOI_1
as an output. (80-pin TQFP only)
16.7
GPIO0_DAT
R, W, 0
GENERAL PURPOSE I/O 0 DATA BIT: When the GPIO0_DIR is
set, this bit reflects the value of the GPIO0 pin. When the
GPIO0_DIR is reset, the value of this bit is driven onto the GPIO0
pin. (80-pin TQFP only)
16.6
GPIO0_DIR
R, W, 1
GENERAL PURPOSE I/O 0 DIRECTION BIT: Setting this bit
configures the GPIO0 pin as an input. Resetting it configures GPIO0
as an output. (80-pin TQFP only)
16.5
APOL
R, W, 0
AUTO POLARITY: During auto-negotiation and 10BASE-T mode,
the 78Q2120 is able to automatically invert the received signal - both
the Manchester data and link pulses - if necessary. Setting this bit
disables this feature.
16.4
RVSPOL
R, (W), 0
REVERSE POLARITY: The reverse polarity is detected either
through 8 inverted 10BASE-T link pulses (NLP) or through one burst
of inverted fast link pulses (FLP). When the reverse polarity is
detected, the 78Q2120 will invert the receive data path and set this
bit to logic one if the feature is not disabled. If
APOL
is a logic 1,
then this bit is write-able. Setting this bit forces the polarity to be
reversed.
16.3:2
RSVD
R,W,0
RESERVED. Must be zero.
相關(guān)PDF資料
PDF描述
78Q2120-64CGT 10/100BASE-TX Ethernet Transceiver
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78Q2120-CGT 10/100BASE-TX Ethernet Transceiver
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相關(guān)代理商/技術(shù)參數(shù)
參數(shù)描述
78Q2120-64CGT 制造商:未知廠家 制造商全稱:未知廠家 功能描述:10/100BASE-TX Ethernet Transceiver
78Q2120-64T 制造商:未知廠家 制造商全稱:未知廠家 功能描述:10/100BASE-TX Ethernet Transceiver
78Q2120C 制造商:TDK 制造商全稱:TDK Electronics 功能描述:10/100BASE - TX Transceiver
78Q2120C09-64CGT 制造商:TERIDIAN 制造商全稱:TERIDIAN 功能描述:10/100BASE-TX Transceiver
78Q2120C09-64CGT/F 功能描述:以太網(wǎng) IC 10-100 Fast Ethernet Transceiver RoHS:否 制造商:Micrel 產(chǎn)品:Ethernet Switches 收發(fā)器數(shù)量:2 數(shù)據(jù)速率:10 Mb/s, 100 Mb/s 電源電壓-最大:1.25 V, 3.45 V 電源電壓-最小:1.15 V, 3.15 V 最大工作溫度:+ 85 C 封裝 / 箱體:QFN-64 封裝:Tray
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