參數(shù)資料
型號： 784214AY
廠商： NEC Corp.
英文描述： MOS INTEGRATED CIRCUIT
中文描述： 馬鞍山集成電路
文件頁數(shù)： 77/100頁
文件大?。?/td> 564K
代理商： 784214AY
Data Sheet U14121EJ2V0DS00
77
μ
PD784214A, 784215A, 784216A, 784217A, 784218A, 784214AY, 784215AY, 784216AY, 784217AY, 784218AY
www.DataSheet4U.com
AC Characteristics
(2) External wait timing
Parameter
Symbol
Conditions
MIN.
TYP.
MAX.
Unit
V
DD
= 5.0 V
±
10%
V
DD
= 3.0 V
±
10%
V
DD
= 2.0 V
±
10%
V
DD
= 5.0 V
±
10%
V
DD
= 3.0 V
±
10%
V
DD
= 2.0 V
±
10%
V
DD
= 5.0 V
±
10%
V
DD
= 3.0 V
±
10%
V
DD
= 2.0 V
±
10%
V
DD
= 5.0 V
±
10%
V
DD
= 3.0 V
±
10%
V
DD
= 2.0 V
±
10%
V
DD
= 5.0 V
±
10%
V
DD
= 3.0 V
±
10%
V
DD
= 2.0 V
±
10%
V
DD
= 5.0 V
±
10%
V
DD
= 3.0 V
±
10%
V
DD
= 2.0 V
±
10%
V
DD
= 5.0 V
±
10%
V
DD
= 3.0 V
±
10%
V
DD
= 2.0 V
±
10%
V
DD
= 5.0 V
±
10%
V
DD
= 3.0 V
±
10%
V
DD
= 2.0 V
±
10%
V
DD
= 5.0 V
±
10%
V
DD
= 3.0 V
±
10%
V
DD
= 2.0 V
±
10%
V
DD
= 5.0 V
±
10%
V
DD
= 3.0 V
±
10%
V
DD
= 2.0 V
±
10%
V
DD
= 5.0 V
±
10%
V
DD
= 3.0 V
±
10%
V
DD
= 2.0 V
±
10%
V
DD
= 5.0 V
±
10%
V
DD
= 3.0 V
±
10%
V
DD
= 2.0 V
±
10%
V
DD
= 5.0 V
±
10%
V
DD
= 3.0 V
±
10%
V
DD
= 2.0 V
±
10%
(2
+
a)T
40
(2
+
a)T
60
(2
+
a)T
300
1.5T
40
1.5T
60
1.5T
260
ns
ns
Input time from address to
WAIT
↓
t
DAWT
ns
ns
ns
Input time from ASTB
↓
to
WAIT
↓
t
DSTWT
ns
(0.5
+
n)T
+
5
(0.5
+
n)T
+
10
(0.5
+
n)T
+
30
ns
ns
Hold time from ASTB
↓
to WAIT
t
HSTWT
ns
(1.5
+
n)T
40
(1.5
+
n)T
60
(1.5
+
n)T
90
T
40
T
60
T
70
ns
ns
Delay time from ASTB
↓
to
WAIT
↑
t
DSTWTH
ns
ns
ns
Input time from RD
↓
to WAIT
↓
t
DRWTL
ns
nT
+
5
nT
+
10
nT
+
30
ns
ns
Hold time from RD
↓
to WAIT
↓
t
HRWT
ns
(1
+
n)T
40
(1
+
n)T
60
(1
+
n)T
90
0.5T
5
0.5T
10
0.5T
30
ns
ns
Delay time from RD
↓
to WAIT
↑
t
DRWTH
ns
ns
ns
Data input time from WAIT
↑
t
DWTID
ns
0.5T
ns
0.5T
0.5T
+
5
0.5T
ns
Delay time from WAIT
↑
to RD
↑
t
DWTR
ns
ns
0.5T
0.5T
+
5
ns
Delay time from WAIT
↑
to WR
↑
t
DWTW
ns
T
40
T
60
T
90
ns
ns
Input time from WR
↓
to WAIT
↓
t
DWWTL
ns
nT
+
5
nT
+
10
nT
+
30
ns
ns
Hold time from WR
↓
to WAIT
t
HWWT
ns
(1
+
n)T
40
(1
+
n)T
60
(1
+
n)T
90
ns
ns
Delay time from WR
↓
to WAIT
↑
t
DWWTH
ns
Remark
T: t
CYK
= 1/f
XX
(f
XX
: main system clock frequency)
a: 1 (during address wait), otherwise, 0
n: Number of wait states (n
≥
0)
相關PDF資料
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