參數(shù)資料
型號: 7542
英文描述: 250mA CMOS LDO, lsupply 1uA and 2% Vout Accuracy, -40C to +125C, 3-SOT-23, T/R
中文描述: 7542群時鐘異步串行I / OApplication注意70K/MAY.22.03
文件頁數(shù): 6/9頁
文件大小: 70K
代理商: 7542
May 2003
7542 Group
Clock Asynchronous Serial I/O (UART)
Page 6 of 8
REJ05B0023-0100Z
Figure 5 Control procedure of transmitter
0
1
10 ms elapsed
(generated by timer)
Y
N
RESET
SEI
CLD
CLT
1 0 0
Y
N
1
0
UART1CON(Address 1B
16
)
Character length: 8 bits
Parity disabled
Stop bit length: 2 bits
T
X
D
1
: CMOS output
Set UART1 control register
0 1
0
0
“07
16
Y
N
N
Set “0” to the communication control port P0
0
.
Y
SIO1CON(Address 1A
16
)
BRG count source: f(X
IN
)/4
Synchronous clock:
BRG output/16
Transmit interrupt source:
When transmit buffer has emptied
Transmit enabled
Receive disabled
UART
Serial I/O1 enabled
Set serial I/O1 control register
BRG1(Address 1C
16
)
Set baud rate generator
Initialization
TB1/RB1(Address 18
16
)
Write the first-byte transmission data to
the transmit/receive buffer register1
TB1/RB1(Address 18
16
)
Write the second-byte transmission data to
the transmit/receive buffer register1
Transmit buffer has emptied
(checked by b0 of SIO1STS
(address 19
16
))
Transmit shift has completed
(checked by b2 of SIO1STS
(address 19
16
))
Transmit buffer has emptied
(checked by b0 of SIO1STS
(address 19
16
))
Set “1” to the communication control port P0
0
.
Set the communication control port P0
0
to the
output mode.
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