參數(shù)資料
型號(hào): 74VHCT126AMTR
廠商: 意法半導(dǎo)體
英文描述: QUAD BUS BUFFERS 3-STATE
中文描述: 四總線緩沖器的三態(tài)
文件頁數(shù): 1/8頁
文件大?。?/td> 60K
代理商: 74VHCT126AMTR
74VHCT126A
QUAD BUS BUFFERS (3-STATE)
PRELIMINARY DATA
March 2000
PIN CONNECTION AND IECLOGIC SYMBOLS
I
HIGHSPEED:t
PD
=5ns(TYP.)atV
CC
=5V
I
LOWPOWERDISSIPATION:
I
CC
=4
μ
A(MAX.) at T
A
=25
o
C
I
COMPATIBLEWITH TTL OUTPUTS:
V
IH
=2V (MIN),V
IL
= 0.8V(MAX)
I
POWERDOWN PROTECTIONON INPUTS&
OUTPUTS
I
SYMMETRICALOUTPUTIMPEDANCE:
|I
OH
| = I
OL
= 8 mA(MIN)
I
BALANCEDPROPAGATIONDELAYS:
t
PLH
t
PHL
I
OPERATINGVOLTAGERANGE:
V
CC
(OPR)= 4.5Vto 5.5V
I
PINANDFUNCTION COMPATIBLEWITH
74SERIES126
I
IMPROVEDLATCH-UP IMMUNITY
I
LOWNOISE:V
OLP
= 0.8V(Max.)
DESCRIPTION
The 74VHCT126A is an advanced high-speed
CMOS QUAD BUS BUFFERS fabricated with
sub-micron silicon gate and double-layer metal
wiring C
2
MOS technology.
This device requires the 3-STATE control input G
to be set low to place the output into the high
impedancestate.
Power down protection is provided on all inputs
and outputs and 0 to 7V can be accepted on
inputs with no regard to the supply voltage. This
device can be used to interface5V to 3V.
All
inputs
and
outputs are
protection circuits against static discharge, giving
them 2KV ESD immunity and transient excess
voltage.
equipped with
SOP
TSSOP
ORDER CODES
TUBE
74VHCT126AM
PACKAGE
SOP
TSSOP
T & R
74VHCT126AMTR
74VHCT126ATTR
1/8
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