參數(shù)資料
型號(hào): 74VHCT132AM
廠商: 意法半導(dǎo)體
英文描述: QUAD 2-INPUT SCHMITT NAND GATE
中文描述: 四2輸入施密特與非門(mén)
文件頁(yè)數(shù): 1/7頁(yè)
文件大?。?/td> 53K
代理商: 74VHCT132AM
74VHCT132A
QUAD 2-INPUT SCHMITT NAND GATE
PRELIMINARY DATA
February 2000
I
HIGHSPEED:t
PD
=6.5ns(TYP.)atV
CC
= 5V
I
LOWPOWERDISSIPATION:
I
CC
=2
μ
A(MAX.) at T
A
=25
o
C
I
TYPICALHYSTERESIS:0.7Vat V
CC
= 4.5V
I
POWERDOWN PROTECTIONON INPUTS&
OUTPUTS
I
SYMMETRICALOUTPUTIMPEDANCE:
|I
OH
| = I
OL
= 8 mA(MIN)
I
BALANCEDPROPAGATIONDELAYS:
t
PLH
t
PHL
I
OPERATINGVOLTAGERANGE:
V
CC
(OPR)= 4.5Vto 5.5V
I
PINANDFUNCTION COMPATIBLEWITH
74SERIES132
I
IMPROVEDLATCH-UP IMMUNITY
I
LOWNOISE:V
OLP
= 0.8V(Max.)
DESCRIPTION
The 74VHCT132A is an advanced high-speed
CMOS QUAD 2-INPUT SCHMITT NAND GATE
fabricated with sub-micron silicon gate
double-layermetal wiring C
2
MOS technology.
Power down protection is provided on all inputs
and outputs and 0 to 7V can be accepted on
and
inputs with no regard to the supply voltage. This
device can be used to interface5V to 3V.
Pin configuration and function are the same as
those of the VHCT00A but the VHCT132A has
hysteresis.
This together with its schmitt trigger function
allows it to be used on line receivers with slow
rise/fall input signals.
All
inputs
and
outputs are
protection circuits against static discharge, giving
them 2KV ESD immunity and transient excess
voltage.
equipped with
PIN CONNECTION AND IEC LOGIC SYMBOLS
SOP
TSSOP
ORDER CODES
TUBE
74VHCT132AM
PACKAGE
SOP
TSSOP
T & R
74VHCT132AMTR
74VHCT132ATTR
1/7
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