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參數(shù)資料
| 型號(hào)： | 74VHC4040MTCX |
| 廠商： | FAIRCHILD SEMICONDUCTOR CORP |
| 元件分類： | 通用總線功能 |
| 英文描述： | Code Hopping Encoder 3.5- 13V, -40C to +85C, 8-SOIC 150mil, TUBE |
| 中文描述： | AHC/VHC/H/U/V SERIES, ASYN NEGATIVE EDGE TRIGGERED 12-BIT UP BINARY COUNTER, PDSO16 |
| 封裝： | 4.40 MM, MO-153, TSSOP-16 |
| 文件頁數(shù)： | 1/7頁 |
| 文件大小： | 67K |
| 代理商： | 74VHC4040MTCX |
August 1993
Revised April 1999
7
1999 Fairchild Semiconductor Corporation
DS011641.prf
www.fairchildsemi.com
74VHC4040
12-Stage Binary Counter
General Description
The VHC4040 is an advanced high-speed CMOS device
fabricated with silicon gate CMOS technology. It achieves
the high-speed operation similar to equivalent Bipolar
Schottky TTL while maintaining the CMOS low power dissi-
pation. The VHC4040 is a 12-stage counter which incre-
ments on the negative edge of the input clock and all
outputs are reset to a low level by applying a logical high
on the reset input. An input protection circuit insures that
0V to 7V can be applied to the inputs without regard to the
supply voltage. This device can be used to interface 5V to
3V systems and two supply systems such as battery
backup. This circuit prevents device destruction due to mis-
matched supply and input voltages.
Features
I
High speed; f
MAX
=
210 MHz at V
CC
=
5V
I
Low power dissipation: I
CC
=
4
μ
A (max) at T
A
=
25
°
C
I
High noise immunity: V
NIH
=
V
NIL
=
28% V
CC
(min)
I
Power down protection is provided on all inputs
I
Wide operating voltage range: V
CC
(opr)
=
2V
5.5V
I
Low noise: V
OLP
=
0.8V (max)
I
Pin and function compatible with 74HC4040
Ordering Code:
Surface mount packages are also available on Tape and Reel. Specify by appending the suffix letter “X” to the ordering code.
Connection Diagram
Pin Descriptions
Order Number
74VHC4040M
74VHC4040MTC
74VHC4040N
Package Number
M16A
MTC16
N16E
Package Description
16-Lead Small Outline Integrated Circuit (SOIC), JEDEC MS-012, 0.150” Narrow
16-Lead Thin Shrink Small Outline Package (TSSOP), JEDEC MO-153, 4.4mm Wide
16-Lead Plastic Dual-In-Line Package (PDIP), JEDEC MS-001, 0.300” Wide
Pin Names
Description
Q
0
–Q
11
CP
Flip-Flop Outputs
Negative Edged Triggered Clock
MR
Master Reset
相關(guān)PDF資料 |
PDF描述 |
|---|---|
| 74VHC4040MX | Code Hopping Encoder 3.5- 13V, 0C to +70C, 8-PDIP, TUBE |
| 74VHC4053 | Dual 2-Line To 4-Line Decoders/Demultiplexers 16-SSOP -40 to 85 |
| 74VHC4053WM | 8-Channel Analog Multiplexer . Dual 4-Channel Analog Multiplexer . Triple 2-Channel Analog Multiplexer |
| 74VHC4053MTC | 8-Channel Analog Multiplexer . Dual 4-Channel Analog Multiplexer . Triple 2-Channel Analog Multiplexer |
| 74VHC4053N | Dual 2-Line To 4-Line Decoders/Demultiplexers 16-SOIC -40 to 85 |
相關(guān)代理商/技術(shù)參數(shù) |
參數(shù)描述 |
|---|---|
| 74VHC4040MX | 功能描述:計(jì)數(shù)器移位寄存器 12-Stage Binary Ctr RoHS:否 制造商:Texas Instruments 計(jì)數(shù)器類型: 計(jì)數(shù)順序:Serial to Serial/Parallel 電路數(shù)量:1 封裝 / 箱體:SOIC-20 Wide 邏輯系列: 邏輯類型: 輸入線路數(shù)量:1 輸出類型:Open Drain 傳播延遲時(shí)間:650 ns 最大工作溫度:+ 125 C 最小工作溫度:- 40 C 封裝:Reel |
| 74VHC4040N | 功能描述:計(jì)數(shù)器 IC 12-Stage Binary Ctr RoHS:否 制造商:NXP Semiconductors 計(jì)數(shù)器類型:Binary Counters 邏輯系列:74LV 位數(shù):10 計(jì)數(shù)法: 計(jì)數(shù)順序: 工作電源電壓:1 V to 5.5 V 工作溫度范圍:- 40 C to + 125 C 封裝 / 箱體:SOT-109 封裝:Reel |
| 74VHC4040N_Q | 功能描述:計(jì)數(shù)器 IC 12-Stage Binary Ctr RoHS:否 制造商:NXP Semiconductors 計(jì)數(shù)器類型:Binary Counters 邏輯系列:74LV 位數(shù):10 計(jì)數(shù)法: 計(jì)數(shù)順序: 工作電源電壓:1 V to 5.5 V 工作溫度范圍:- 40 C to + 125 C 封裝 / 箱體:SOT-109 封裝:Reel |
| 74VHC4046 | 制造商:FAIRCHILD 制造商全稱:Fairchild Semiconductor 功能描述:CMOS Phase Lock Loop |
| 74VHC4046_03 | 制造商:FAIRCHILD 制造商全稱:Fairchild Semiconductor 功能描述:CMOS Phase Lock Loop |
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