參數(shù)資料
型號: 74VHC393SJX
廠商: FAIRCHILD SEMICONDUCTOR CORP
元件分類: 通用總線功能
英文描述: Asynchronous Up Counter
中文描述: AHC/VHC SERIES, ASYN NEGATIVE EDGE TRIGGERED 4-BIT UP BINARY COUNTER, PDSO14
封裝: 5.30 MM, EIAJ TYPE 2, SOP-14
文件頁數(shù): 1/7頁
文件大?。?/td> 84K
代理商: 74VHC393SJX
March 1993
Revised March 1999
7
1999 Fairchild Semiconductor Corporation
DS011571.prf
www.fairchildsemi.com
74VHC393
Dual 4-Bit Binary Counter
General Description
The VHC393 is an advanced high speed CMOS 4-bit
Binary Counter fabricated with silicon gate CMOS technol-
ogy. It achieves the high speed operation similar to equiva-
lent Bipolar Schottky TTL while maintaining the CMOS low
power dissipation. It contains two independent counter cir-
cuits in one package, so that counting or frequency division
of 8 binary bits can be achieved with one IC. This device
changes state on the negative going transition of the
CLOCK
pulse. The counter can be reset to “0” (Q
0
–Q
3
=
“L”) by a HIGH at the CLEAR input regardless of other
inputs.
An input protection circuit ensures that 0V to 7V can be
applied to the input pins without regard to the supply volt-
age. This device can be used to interface 5V to 3V systems
and two supply systems such as battery back up. This cir-
cuit prevents device destruction due to mismatched supply
and input voltages.
Features
I
High Speed: f
MAX
=
170 MHz (typ) at T
A
=
25
°
C
I
Low power dissipation: I
CC
=
4
μ
A (max) at T
A
=
25
°
C
I
High noise immunity: V
NIH
=
V
NIL
=
28% V
CC
(min)
I
Power down protection is provided on all inputs
I
Pin and function compatible with 74HC393
Ordering Code:
Surface mount packages are also available on Tape and Reel. Specify by appending the suffix letter “X” to the ordering code.
Logic Symbol
IEEE/IEC
Connection Diagram
Pin Descriptions
Order Number
74VHC393M
74VHC393SJ
74VHC393MTC
74VHC393N
Package Number
M14A
M14D
MTC14
N14A
Package Description
14-Lead Small Outline Integrated Circuit (SOIC), JEDEC MS-120, 0.150” Narrow
14-Lead Small Outline Package (SOP), EIAJ TYPE II, 5.3mm Wide
14-Lead Thin Shrink Small Outline Package (TSSOP), JEDEC MO-153, 4.4mm Wide
14-Lead Plastic Dual-In-Line Package (PDIP), JEDEC MS-001, 0.300 Wide
Pin Names
Description
CLR1, CLR2
Clear Inputs
CP
1
, CP
2
QA, QB, QC, QD
Clock Pulse Inputs
Outputs
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