參數(shù)資料
型號: 74VHC374SJX
廠商: FAIRCHILD SEMICONDUCTOR CORP
元件分類: 通用總線功能
英文描述: Octal D-Type Flip-Flop
中文描述: AHC/VHC SERIES, 8-BIT DRIVER, TRUE OUTPUT, PDSO20
封裝: 5.30 MM, LEAD FREE, EIAJ TYPE2, SOP-20
文件頁數(shù): 4/10頁
文件大小: 75K
代理商: 74VHC374SJX
CAPACITIVE CHARACTERISTICS
Symbol
Parameter
Test Conditions
Value
Unit
T
A
= 25
o
C
Min.
Typ.
-40 to 85
o
C
Min.
Max.
10
Max.
10
C
IN
C
OUT
C
PD
Input Capacitance
Output Capacitance
Power Dissipation
Capacitance (note 1)
4
6
pF
pF
pF
32
1)C
PD
isdefined as thevalue oftheIC’sinternal equivalent capacitance whichiscalculated fromtheoperatingcurrent consumption without load.(Referto
TestCircuit).Average operatingcurrent canbeobtained bythefollowingequation.I
CC
(opr)=C
PD
V
CC
f
IN
+I
CC
/8(per Flip-Flop)
AC ELECTRICAL CHARACTERISTICS
(Inputt
r
= t
f
=3 ns)
Symbol
Parameter
Test Condition
C
L
(pF)
3.3
(*)
15
3.3
(*)
50
5.0
(**)
15
5.0
(**)
50
3.3
(*)
15
3.3
(*)
50
5.0
(**)
15
5.0
(**)
50
3.3
(*)
50
5.0
(**)
50
3.3
(*)
5.0
(**)
3.3
(*)
5.0
(**)
3.3
(*)
5.0
(**)
3.3
(*)
5.0
(**)
3.3
(*)
50
5.0
(**)
50
Value
Unit
V
CC
(V)
T
A
= 25
o
C
Min.
Typ.
-40 to 85
o
C
Min.
1.0
1.0
1.0
1.0
1.0
1.0
1.0
1.0
1.0
1.0
Max.
12.7
16.2
8.1
10.1
11.0
14.5
7.6
9.6
14.0
8.8
5.0
5.0
4.5
3.0
2.0
2.0
Max.
15.0
18.5
9.5
11.5
13.0
16.5
9.0
11.0
16.0
10.0
5.5
5.0
4.5
3.0
2.0
2.0
t
PLH
t
PHL
Propagation Delay
Time
CK to Q
8.1
10.6
5.4
6.9
7.1
9.6
5.1
6.6
10.2
6.1
ns
t
PZL
t
PZH
Output EnableTime
R
L
= 1K
R
L
= 1K
R
L
= 1K
R
L
= 1K
R
L
= 1K
R
L
= 1K
ns
t
PLZ
t
PHZ
Output Disable Time
ns
t
w
Clock Pulse Width
HIGH or LOW
ns
t
s
Setup Time D to CK
HIGH or LOW
ns
t
h
Hold Time D to CK
HIGH or LOW
ns
f
MAX
Maximum Clock
Frequency
60
100
250
270
60
100
MHz
t
OSLH
t
OSHL
Output to Output Skew
Time (note 1)
(*) Voltagerangeis3.3V
±
0.3V
(**) Voltagerange is 5V
±
0.5V
Note1:Parameter guaranteed bydesign. t
soLH
=|t
pLHm
-t
pLHn
|,t
soHL
=|t
pHLm
-t
pHLn
|
1.5
1.0
1.5
1.0
ns
74VHC374
4/10
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