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參數(shù)資料
| 型號： | 74VHC373M |
| 廠商： | 意法半導體 |
| 元件分類： | 通用總線功能 |
| 英文描述： | OCTAL D-TYPE LATCH WITH 3 STATE OUTPUT NON INVERTING |
| 中文描述： | 八路D型，3態(tài)輸出的非反相鎖存 |
| 文件頁數(shù)： | 1/10頁 |
| 文件大?。?/td> | 75K |
| 代理商： | 74VHC373M |
74VHC373
OCTAL D-TYPE LATCH
WITH 3 STATE OUTPUT NON INVERTING
June 1999
I
HIGHSPEED:t
PD
=5.0ns(TYP.)atV
CC
= 5V
I
LOWPOWERDISSIPATION:
I
CC
=4
μ
A(MAX.) at T
A
=25
o
C
I
HIGHNOISEIMMUNITY:
V
NIH
= V
NIL
=28%V
CC
(MIN.)
I
POWERDOWN PROTECTIONON INPUTS
I
SYMMETRICALOUTPUTIMPEDANCE:
|I
OH
| = I
OL
= 8 mA(MIN)
I
BALANCEDPROPAGATIONDELAYS:
t
PLH
t
PHL
I
OPERATINGVOLTAGERANGE:
V
CC
(OPR)= 2Vto 5.5V
I
PINANDFUNCTION COMPATIBLEWITH
74SERIES373
I
IMPROVEDLATCH-UP IMMUNITY
I
LOWNOISE:V
OLP
= 0.9V(Max.)
DESCRIPTION
The 74VHC373 is an advanced high-speed
CMOS OCTAL D-TYPE LATCH with 3 STATE
OUTPUT
NON
INVERTING
sub-micron silicon gate and double-layer metal
wiring C
2
MOS technology.
This 8 bit D-Type latch is controlled by a latch
enable input (LE) and an output enable input
(OE).
fabricated
with
While the LE input is held at a high level, the Q
outputswill follow the datainputs precisely. When
the LE is taken low, the Q outputs will be latched
precisely at the logic level of D input data. While
the (OE) input is low, the 8 outputs will be in a
normal logic state (high or low logic level) and
while high level the outputs will be in a high
impedancestate.
Power down protection is provided on all inputs
and 0 to 7V can be accepted on inputs with no
regard to the supply voltage. This device can be
used to interface5V to 3V.
All
inputs
and
outputs are
protection circuits against static discharge, giving
them 2KV ESD immunity and transient excess
voltage.
equipped with
PIN CONNECTION AND IEC LOGIC SYMBOLS
ORDER CODES :
74VHC373M
74VHC373T
M
(Micro Package)
T
(TSSOPPackage)
1/10
相關PDF資料 |
PDF描述 |
|---|---|
| 74VHC373T | OCTAL D-TYPE LATCH WITH 3 STATE OUTPUT NON INVERTING |
| 74VHC373 | Octal D-Type Latch with 3-STATE Outputs |
| 74VHC373M | Octal D-Type Latch with 3-STATE Outputs |
| 74VHC373MTC | Octal D-Type Latch with 3-STATE Outputs |
| 74VHC373N | Octal D-Type Latch with 3-STATE Outputs |
相關代理商/技術參數(shù) |
參數(shù)描述 |
|---|---|
| 74VHC373M_07 | 制造商:FAIRCHILD 制造商全稱:Fairchild Semiconductor 功能描述:Octal D-Type Latch with 3-STATE Outputs |
| 74VHC373M_Q | 功能描述:閉鎖 Octal D-Type Latch RoHS:否 制造商:Micrel 電路數(shù)量:1 邏輯類型:CMOS 邏輯系列:TTL 極性:Non-Inverting 輸出線路數(shù)量:9 高電平輸出電流: 低電平輸出電流: 傳播延遲時間: 電源電壓-最大:12 V 電源電壓-最小:5 V 最大工作溫度:+ 85 C 最小工作溫度:- 40 C 封裝 / 箱體:SOIC-16 封裝:Reel |
| 74VHC373MTC | 功能描述:閉鎖 Octal D-Type Latch RoHS:否 制造商:Micrel 電路數(shù)量:1 邏輯類型:CMOS 邏輯系列:TTL 極性:Non-Inverting 輸出線路數(shù)量:9 高電平輸出電流: 低電平輸出電流: 傳播延遲時間: 電源電壓-最大:12 V 電源電壓-最小:5 V 最大工作溫度:+ 85 C 最小工作溫度:- 40 C 封裝 / 箱體:SOIC-16 封裝:Reel |
| 74VHC373MTC_07 | 制造商:FAIRCHILD 制造商全稱:Fairchild Semiconductor 功能描述:Octal D-Type Latch with 3-STATE Outputs |
| 74VHC373MTC_Q | 功能描述:閉鎖 Octal D-Type Latch RoHS:否 制造商:Micrel 電路數(shù)量:1 邏輯類型:CMOS 邏輯系列:TTL 極性:Non-Inverting 輸出線路數(shù)量:9 高電平輸出電流: 低電平輸出電流: 傳播延遲時間: 電源電壓-最大:12 V 電源電壓-最小:5 V 最大工作溫度:+ 85 C 最小工作溫度:- 40 C 封裝 / 箱體:SOIC-16 封裝:Reel |
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