參數(shù)資料
型號(hào): 74VHC373
廠商: Fairchild Semiconductor Corporation
英文描述: Octal D-Type Latch with 3-STATE Outputs
中文描述: 八路D類鎖存器與三態(tài)輸出
文件頁數(shù): 1/10頁
文件大小: 75K
代理商: 74VHC373
74VHC373
OCTAL D-TYPE LATCH
WITH 3 STATE OUTPUT NON INVERTING
June 1999
I
HIGHSPEED:t
PD
=5.0ns(TYP.)atV
CC
= 5V
I
LOWPOWERDISSIPATION:
I
CC
=4
μ
A(MAX.) at T
A
=25
o
C
I
HIGHNOISEIMMUNITY:
V
NIH
= V
NIL
=28%V
CC
(MIN.)
I
POWERDOWN PROTECTIONON INPUTS
I
SYMMETRICALOUTPUTIMPEDANCE:
|I
OH
| = I
OL
= 8 mA(MIN)
I
BALANCEDPROPAGATIONDELAYS:
t
PLH
t
PHL
I
OPERATINGVOLTAGERANGE:
V
CC
(OPR)= 2Vto 5.5V
I
PINANDFUNCTION COMPATIBLEWITH
74SERIES373
I
IMPROVEDLATCH-UP IMMUNITY
I
LOWNOISE:V
OLP
= 0.9V(Max.)
DESCRIPTION
The 74VHC373 is an advanced high-speed
CMOS OCTAL D-TYPE LATCH with 3 STATE
OUTPUT
NON
INVERTING
sub-micron silicon gate and double-layer metal
wiring C
2
MOS technology.
This 8 bit D-Type latch is controlled by a latch
enable input (LE) and an output enable input
(OE).
fabricated
with
While the LE input is held at a high level, the Q
outputswill follow the datainputs precisely. When
the LE is taken low, the Q outputs will be latched
precisely at the logic level of D input data. While
the (OE) input is low, the 8 outputs will be in a
normal logic state (high or low logic level) and
while high level the outputs will be in a high
impedancestate.
Power down protection is provided on all inputs
and 0 to 7V can be accepted on inputs with no
regard to the supply voltage. This device can be
used to interface5V to 3V.
All
inputs
and
outputs are
protection circuits against static discharge, giving
them 2KV ESD immunity and transient excess
voltage.
equipped with
PIN CONNECTION AND IEC LOGIC SYMBOLS
ORDER CODES :
74VHC373M
74VHC373T
M
(Micro Package)
T
(TSSOPPackage)
1/10
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PDF描述
74VHC373M Octal D-Type Latch with 3-STATE Outputs
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74VHC373N Octal D-Type Latch with 3-STATE Outputs
74VHC373SJ Quadruple Bus Buffer Gates With 3-State Outputs 14-PDIP -40 to 85
74VHC374 OCTAL D-TYPE FLIP FLOP WITH 3 STATE OUTPUT NON INVERTING
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