參數(shù)資料
型號: 74VHC16240
廠商: 意法半導體
英文描述: 16-BIT BUS BUFFER WITH 3-STATE OUTPUTS (INVERTED)
中文描述: 16位總線緩沖區(qū)三態(tài)輸出(逆向)
文件頁數(shù): 1/10頁
文件大?。?/td> 149K
代理商: 74VHC16240
1/10
February 2003
I
HIGH SPEED: t
PD
= 5.3 ns (TYP.) at V
CC
= 5V
LOW POWER DISSIPATION:
I
CC
= 4
μ
A (MAX.) at T
A
=25°C
HIGH NOISE IMMUNITY
V
NIH
=V
NIL
= 28% VCC (MIN.)
POWER DOWN PROTECTION ON INPUTS
& OUTPUTS
SYMMETRICAL OUTPUT IMPEDANCE:
|I
OH
| = I
OL
= 8 mA (MIN)
BALANCED PROPAGATION DELAYS:
t
PLH
t
PHL
OPERATING VOLTAGE RANGE:
V
CC
(OPR) = 2V to 5.5V
IMPROVED LATCH-UP IMMUNITY
LOW NOISE: V
OLP
= 0.9V (MAX.)
I
I
I
I
I
I
I
I
DESCRIPTION
The 74VHC16240 is an advanced high-speed
CMOS
16-BIT
BUS
fabricated
with
sub-micron
double-layer metal wiring C
2
MOS technology.
Any
nG
output
control
BUFFERS.
Output
Enable
together give full 16 bit operation.
When nG is LOW, the outputs are on. When nG is
HIGH, the output are in high impedance state.
This device is designed to be used with 3 state
memory address drivers, etc.
Power down protection is provided on all inputs
and outputs and 0 to 7V can be accepted on
inputs with no regard to the supply voltage. This
device can be used to interface 5V to 3V.
All
inputs
and
outputs
protection circuits against static discharge, giving
them 2KV ESD immunity and transient excess
voltage.
BUFFER
silicon
(3-STATE)
gate
and
governs
inputs
four
(nG)
BUS
tied
are
equipped
with
74VHC16240
16-BIT BUS BUFFER
WITH 3-STATE OUTPUTS (INVERTED)
ORDER CODES
PACKAGE
TUBE
T & R
TSSOP
74VHC16240TTR
TSSOP
PIN CONNECTION
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