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參數(shù)資料
| 型號(hào)： | 74VHC16245TTR |
| 廠商： | 意法半導(dǎo)體 |
| 元件分類： | 通用總線功能 |
| 英文描述： | 16-BIT BUS TRANSCEIVER |
| 中文描述： | 16位總線收發(fā)器 |
| 文件頁數(shù)： | 1/10頁 |
| 文件大?。?/td> | 249K |
| 代理商： | 74VHC16245TTR |
1/10
July 2003
I
HIGH SPEED: t
PD
= 4.0 ns (TYP.) at V
CC
= 5V
LOW POWER DISSIPATION:
I
CC
= 4
μ
A (MAX.) at T
A
=25°C
HIGH NOISE IMMUNITY
V
NIH
=V
NIL
= 28% VCC (MIN.)
POWER DOWN PROTECTION ON INPUTS
& OUTPUTS
SYMMETRICAL OUTPUT IMPEDANCE:
|I
OH
| = I
OL
= 8 mA (MIN)
BALANCED PROPAGATION DELAYS:
t
PLH
t
PHL
OPERATING VOLTAGE RANGE:
V
CC
(OPR) = 2V to 5.5V
IMPROVED LATCH-UP IMMUNITY
LOW NOISE: V
OLP
= 0.9V (MAX.)
I
I
I
I
I
I
I
I
DESCRIPTION
The 74VHC16245 is an advanced high-speed
CMOS 16-BIT BUS TRANSCEIVER (3-STATE)
fabricated
with
sub-micron
double-layer metal wiring C
2
MOS technology.
This IC is intended for two-way asynchronous
communication
between
direction of data transmission is determined by
DIR input. The enable input G can be used to
disable the device so that the busses are
effectively isolated.
All
inputs
and
outputs
protection circuits against static discharge, giving
them 2KV ESD immunity and transient excess
voltage.
All floating bus terminals during High Z State must
be held HIGH or LOW.
silicon
gate
and
data
busses;
the
are
equipped
with
74VHC16245
16-BIT BUS TRANSCEIVER
WITH 3-STATE OUTPUTS (NON INVERTED)
ORDER CODES
PACKAGE
TUBE
T & R
TSSOP
74VHC16245TTR
TSSOP
PIN CONNECTION
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